|Category||Logic => Latches => CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage|
|Title||CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage|
|Description||Low Voltage 16-Bit Transparent Latch With 5V Tolerant Inputs And Outputs|
|Datasheet||Download 74LCX16373 datasheet
|Cross ref.||Similar parts: 74LCX16373AT, 74LCX16373T, PI74LCX16373A|
|74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
The LCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LCX16373 is designed for low voltage or 3.3V) VCC applications with capability of interfacing a 5V signal environment. The LCX16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.Features
s 5V tolerant inputs and outputs s 2.3V3.6V VCC specifications provided 5.4 ns tPD max (VCC 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note ±24 mA output drive (VCC 3.0V) s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds mA s ESD performance: Human body model > 2000V Machine model 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Order Number 74LCX16373G (Note 3) 74LCX16373MEA (Note 3) 74LCX16373MTD (Note 3) Package Number MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering code "G" indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pin Names OEn LEn O0O15 NC Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs No Connect
Inputs LE1 X Pin Assignment for FBGA L OE1 Inputs LE2 (Top Thru View) I8I15 I0I7 Outputs H O0 Outputs H O0
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
The LCX16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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