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Part: 74LCX760MSA
Category:
Description: 74LCX760 - Low Voltage Buffer/line Driver With 5V Tolerant Inputs And Open Drain Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74LCX760MSA datasheet File size : 201 kB
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Datasheet text preview:
74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs
July 2001 Revised February 2002
74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs
General Description
The LCX760 is the Open Drain version of the LCX244. The LCX760 contains eight non-inverting buffers with 3-STATE outputs. The device may be employed as a memory address driver, clock driver and bus-oriented transmitter/ receiver. The LCX760 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX760 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s Open drain version of the LCX244 s 5V tolerant inputs and outputs s 2.3V3.6V VCC specifications provided s 8.0 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s 24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX760WM 74LCX760SJ 74LCX760MSA 74LCX760MTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 4.4mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
© 2002 Fairchild Semiconductor Corporation
DS500413
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74LCX760
Pin Descriptions
Pin Names OE1, OE2 I0I7 O0O7 Description 3-STATE Output Enable Inputs Inputs Outputs
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Outputs In L H X (Pins 12, 14, 16, 18) L H Z Outputs In L H X (Pins 3, 5, 7, 9) L H Z
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74LCX760
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in HIGH or LOW State (Note 3) VI VCC V mA mA mA mA mA
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -5 0 -5 0 +5 0
50
±100 ±100 -65 to +150
°C
Recommended Operating Conditions (Note 4)
Symbol VC C VI VO I OL Supply Voltage Input Voltage Output Voltage Output Current VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 Max 3.6 3.6 5.5 5.5 24 12 8 mA Units V V V
-40
0
85 10
°C
ns/V
t/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused inputs or I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOL Parameter HIGH Level Input Voltage LOW Level Input Voltage LOW Level Output Voltage IOL = 100 µA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF ICC ICC IOHZ Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input Off State Current 0 VI 5.5V 0 VO 5.5V VI = V IH or VIL VI or VO = 5.5V VI = V CC or GND 3.6V VI, VO 5.5V (Note 5) VIH = VCC -0.6V VO = 5.5 Conditions VCC (V) 2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 0 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 2 - 3.6 TA = -40°C to +85°C M in 1 .7 2 .0 0 .7 0 .8 0 .2 0 .6 0 .4 0 .4 0.55 ±5.0 ±5.0 10 10 ±10 500 10 µA µA µA µA µA µA V Max V V Units
Note 5: Outputs disabled or 3-STATE only.
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74LCX760
AC Electrical Characteristics
TA = -40°C to +85°C, RL = 500 Symbol Parameter VCC = 3.3V ± 0.3V CL= 50 pF Min tPZL tPLZ tPZL tPLZ tOSHL tOSLH Propagation Delay Data to Output Output Enable Time OEn to Out Output Disable Time OEn to Out Output to Output Skew (Note 6) 0.5 0.5 0.5 0.5 Max 8.0 7 .0 8.0 7 .0 1.0 1.0 VCC = 2.7V CL = 50 pF Min 0.5 0.5 0.5 0.5 Max 9.0 8.0 9.0 8.0 VCC = 2.5V ± 0.2 CL = 30 pF Min 0.5 0.5 0.5 0.5 M ax 10.0 8 .4 10.0 8 .4 ns ns ns ns Units
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25°C Typical 0 .8 0 .6 -0.8 -0.6 V V Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 10 Units pF pF pF
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74LCX760
AC LOADING and WAVEFORMS
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPZL, tPLZ Switch 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vm o Vx Vy VC C 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
trise and tfall
2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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