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Details, datasheet, quote on part number:74LVT16245MTDX
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Datasheet text preview:
74LVT16245 · 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs
January 1999 Revised August 2001
74LVT16245 · 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVTH16245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16245 and LVTH16245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16245), also available without bushold feature (74LVT16245). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 16245 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model >2000V Machine model >200V Charged-device >1000V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Ordering Code:
Order Number 74LVT16245GX (Note 1) 74LVT16245MEA (Note 2) 74LVT16245MTD (Note 2) 74LVTH16245GX (Note 1) 74LVTH16245MEA (Note 2) 74LVTH16245MTD (Note 2) Package Number BGA54A (Preliminary) MS48A MTD48 BGA54A (Preliminary) MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500152
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74LVT16245 · 74LVTH16245
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn T/Rn A0A15 B0B15 NC Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J B0 B2 B4 B6 B8 B1 0 B1 2 B1 4 B1 5 2 NC B1 B3 B5 B7 B9 B11 B1 3 NC 3 T/R1 NC VC C G ND G ND G ND VC C NC T/R2 4 OE1 NC VC C GND GND GND VC C NC OE2 5 NC A1 A3 A5 A7 A9 A11 A1 3 NC 6 A0 A2 A4 A6 A8 A1 0 A1 2 A1 4 A1 5
Truth Tables
Inputs Pin Assignment for FBGA OE1 L L H Inputs OE2 L L H (Top Thru View) T/R2 L H X Outputs Bus B8B15 Data to Bus A8A15 Bus A8A15 Data to Bus B8B15 HIGHZ State on A8A15,B8B15 T/R1 L H X Outputs Bus B0B7 Data to Bus A0A7 Bus A0A7 Data to Bus B0B7 HIGHZ State on A0A7,B0B7
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
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74LVT16245 · 74LVTH16245
Functional Description
The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Logic Diagrams
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT16245 · 74LVTH16245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI VCC Output at LOW State, VO > VCC V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
±64 ±128 -65 to +150
°C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-3 2
64
-40
0
+8 5
10
°C
ns/V
t/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Ratings must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.73.6 2.73.6 2.73.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZL (Note 5) Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Bushold Input Minimum Drive 3.0 3.0 3.6 3.6 3.6 0 01.5 3.6 3.6 75 - 75 500 -500 10 ±1 -5 1 ±100 ±100 -5 -5 µA µA µA µA µA VCC - 0.2 2 .4 2 .0 0 .2 0 .5 0 .4 0 .5 0 .5 5 µA µA V V 2 .0 0 .8 TA = -40°C to +85°C M in Max -1.2 Units V V V Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 µA IOH = -8 mA IOH = -32 mA IOL = 100 µA IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 6) (Note 7) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 0.0V
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74LVT16245 · 74LVTH16245
DC Electrical Characteristics
Symbol IOZH IOZH (Note 5) IOZH+ ICCH ICCL ICCZ ICCZ+ ICC (Note 8)
Note 5: Applies to bushold versions only (74LVTH16245).
(Continued)
VCC (V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 TA = -40°C to +85°C M in Max 5 5 10 0.19 5.0 0.19 0.19 0.2 µA µA µA mA mA mA mA mA VO = 3.0V VO = 3.6V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Parameter 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current
Units
Conditions
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL V CC (V) 3.3 3.3
(Note 9)
TA = 25°C Units V V Conditions CL = 50 pF, RL = 500 (Note 10) (Note 10)
Min
Typ 0.8 -0.8
M ax
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40°C to +85°C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3V ± 0.3V M in tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 11) Output Disable Time Output Enable Time Propagation Delay Data to Output 1.5 1.3 1.5 1.6 2.3 2.2 Max 3.5 3 .5 4 .5 5 .3 5 .4 5 .1 1.0 VCC = 2.7V Min 1.5 1.3 1.5 1.6 2.3 2.2 Max 3.9 3.9 5.3 6.9 6.1 5.4 1.0 ns ns ns ns Units
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol CIN CI/O
(Note 12)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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