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Details, datasheet, quote on part number:74LVX161284MTD
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Datasheet text preview:
74LVX161284 Low Voltage IEEE 161284 Translating Transceiver
January 1999 Revised November 2000
74LVX161284 Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (VCCcable) to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCcable supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1A8/B1B8 transceiver pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s Translation capability allows outputs on the cable side to interface with 5V signals s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interface between the "Peripheral and Host" s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number 74LVX161284MEA 74LVX161284MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names HD DIR A1A8 B1B8 A9A13 Y9Y13 A14A17 C14C17 PLHIN PLH HLHIN HLH Description High Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output
© 2000 Fairchild Semiconductor Corporation
DS500202
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74LVX161284
Logic Symbol
Truth Table
Inputs DIR L HD L B1B8 Data to A1A8, and A9A13 Data to Y9Y13 (Note 1) C14C17 Data to A14A17 PLH Open Drain Mode L H B1B8 Data to A1A8, and A9A13 Data to Y9Y13 C14C17 Data to A14A17 H L A1A8 Data to B1B8 (Note 2) A9A13 Data to Y9Y13 (Note 1) C14C17 Data to A14A17 PLH Open Drain Mode H H A1A8 Data to B1B8 A9A13 Data to Y9Y13 C14C17 Data to A14A17
Note 1: Y9Y13 Open Drain Outputs Note 2: B1B8 Open Drain Outputs
Outputs
Logic Diagram
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74LVX161284
Absolute Maximum Ratings(Note 3)
Supply Voltage VC C VCC--Cable VCC--Cable Must Be VCC Input Voltage (VI)--(Note 4) A1A13, PLHIN , DIR, HD B1B8, C14C17, HLHIN B1B8, C14C17, HLHIN Output Voltage (VO) A1A8, A14A17, HLH B1B8, Y9Y13, PLH B1B8, Y9Y13, PLH DC Output Current (IO) A1A8, HLH B1B8, Y9Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK)--(Note 4) DIR, HD, A9A13, PLH, HLH, C14C17 Output Diode Current (IOK) A1A8, A14A17, HLH B1B8, Y9Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD (HBM) Last Passing Voltage
Recommended Operating Conditions
Supply Voltage VC C VCC--Cable DC Input Voltage (VI) Open Drain Voltage (VO) Operating Temperature (TA) 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V
-0.5V to +4.6V -0.5V to +7.0V
-0.5V to VCC + 0.5V -0.5V to +5.5V (DC) -2.0V to +7.0V*
*40 ns Transient
-40°C to +85°C
-0.5V to VCC +0.5V -0.5V to +5.5V (DC) -2.0V to +7.0V*
*40 ns Transient
±25 mA ±50 mA
84 mA
-50 mA -20 mA ±50 mA -50 mA ±200 mA -65°C to +150°C
2000V
Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Fairchild does not recommend operation outside the databook specifications. Note 4: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VT Minimum Input Hysteresis VOH Minimum HIGH Level Output Voltage Bn, Yn Bn, Yn PLH An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, HLH 3.03.6 3.03.6 3.03.6 3.03.6 3.03.6 3.03.6 3.3 3.3 3.3 3 .0 3.0 3.0 3.0 3.15 3.05.5 3.05.5 3.05.5 3.05.5 3.05.5 3.05.5 5 .0 5 .0 5 .0 3.0 3 .0 3 .0 4.5 3 .15 2 .0 2 .3 2 .6 0 .8 0 .8 1 .6 0.4 0.8 0.2 2 .8 2.4 2.0 2.23 3 .1 2.0 2.3 2.6 0.8 0.8 1.6 0 .4 0 .8 0 .2 2.8 2 .4 2 .0 2.23 3.1 V V VT+VT- VT+VT- VT+VT- IOH = -50 µA IOH = -4 mA IOH = -14 mA IOH = -14 mA IOH = -500 µA V V Parameter VCC (V) 3.0 VCC--Cable (V) 3 .0 TA = 0°C to +70°C -1.2 TA = -40°C to +85°C -1.2 Units V Conditions Ii= -18 mA
Guaranteed Limits
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74LVX161284
DC Electrical Characteristics
Symbol VOL Maximum LOW Level Output Voltage Bn, Yn Bn, Yn P LH P LH RD Maximum Output Impedance Minimum Output Impedance RP Maximum Pull-Up Resistance Minimum Pull-Up Resistance IIH Maximum Input Current in HIGH State IIL Maximum Input Current in LOW State IOZH Maximum Output Disable Current (HIGH) IOZL Maximum Output Disable Current (LOW) IOFF IOFF IOFF--ICC Power Down Output Leakage Power Down Input Leakage Power Down Leakage to VCC IOFF--ICC2 Power Down Leakage to VCC--Cable ICC Maximum Supply Current B1B8, Y9Y13, C14C17 B1B8, Y9Y13 C14C17 A9A13, PLHIN, HD, DIR, HLHIN C14C17 C14C17 A9A13, PLHIN, HD, DIR, HLHIN C14C17 C14C17 A1A8 B1B8 B1B8 A1A8 B1B8 B1B8 B1B8, Y9Y13, P LH C14C17, HLHIN B1B8, Y9Y13 B1B8, Y9Y13 Parameter An, HLH
(Continued)
TA = 0°C to +70°C 0 .2 0.4 0.8 0.77 0 .85 0 .8 60 55 30 35 1650 1650 1150 1150 1 .0 50.0 100 - 1.0 - 3.5 - 5.0 20 50 100 - 20 - 3.5 - 5.0 100 100 250 250 45 70 TA = -40°C to +85°C 0.2 0 .4 0 .8 0.77 0 .95 0.9 60 55 30 35 1650 1650 1150 1150 1.0 50.0 100 -1.0 -3.5 -5.0 20 50 100 - 20 -3.5 -5.0 100 100 250 250 45 70 µA mA mA µA µA µA µA mA mA µA µA µA µA mA mA VO = 5.5V VI = 5.5V (Note 6) (Note 6) VI = VCC or GND VI = VCC or GND µA VI = 3.6V VI = 3.6V VI = 5.5V VI = 0.0V VI = 0.0V VI = 0.0V VO = 3.6V VO = 3.6V VO = 5.5V VO = 0.0V (Note 5)(Note 7) V Units Conditions IOL = 50 µA IOL = 4 mA IOL = 14 mA IOL = 14 mA IOL = 84 mA IOL = 84 mA (Note 5)(Note 7)
VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.0 0.0 0.0 0.0 3.6 3.6
VCC--Cable (V) 3.0 3 .0 3 .0 4.5 3.0 4.5 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.6 3.6 5.5 3 .6 3 .6 5 .5 3.6 3.6 5.5 3 .6 3 .6 5 .5 0.0 0.0 0.0 0.0 3.6 5.5
Guaranteed Limits
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH). Note 6: Power-down leakage to VCC or VCC--Cable is tested by simultaneously forcing all pins on the cable-side (B1B8, Y9Y13, PLH, C14C17 and HLHIN) to 5.5V and measuring the resulting ICC or ICC--Cable. Note 7: This parameter is guaranteed but not tested, characterized only.
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74LVX161284
AC Electrical Characteristics
TA = 0°C to +70°C Symbol Parameter VCC = 3.0V3.6V VCC--Cable = 3.0V5.5V Min tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tSKEW tPHL tPLH tPHL tPLH tPHZ tPLZ tPZH tPZL tPHZ tPLZ tpEN tpDIS tpENtpDIS tSLEW tPLH tPHL tr, tf tRISE and tFALL B1B8 (Note 8), Y9Y13 (Note 8)
Note 8: Open Drain Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type: (i) A1A8 to B1B8, A9A13 to Y9Y13 (ii) B1B8 to A1A8 (iii) C14C17 to A14A17 Note 10: This parameter is guaranteed but not tested, characterized only.
TA = -40°C to +85°C VCC = 3.0V3.6V VCC--Cable = 3.0V5.5V Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2 .0 2 .0 2.0 2 .0 2 .0 2 .0 2.0 2 .0 2 .0 2 .0 Max 44.0 44.0 44.0 44.0 44.0 44.0 44.0 44.0 12.0 44.0 44.0 44.0 44.0 18.0 18.0 50.0 50.0 50.0 50.0 28.0 28.0 28.0 28.0 12.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 3 Figure 3 Figure 1 Figure 2 Figure 3 Figure 3 (Note 9) Figure 1 Figure 2 Figure 3 Figure 3 Figure 7 Figure 8 Figure 9 Figure 2 Figure 2 Units Figure Number
Max 40.0 40.0 40.0 40.0 40.0 40.0 40.0 40.0 10.0 40.0 40.0 40.0 40.0 15.0 15.0 50.0 50.0 50.0 50.0 25.0 25.0 25.0 25.0 10.0
A1A8 to B1B8 A1A8 to B1B8 B1B8 to A1A8 B1B8 to A1A8 A9A13 to Y9Y13 A9A13 to Y9Y13 C14C17 to A14A17 C14C17 to A14A17 LH-LH or HL-HL PLHIN to PLH PLHIN to PLH HLHIN to HLH HLHIN to HLH Output Disable Time DIR to A1A8 Output Enable Time DIR to A1A8 Output Disable Time DIR to B1B8 Output Enable Time HD to B1B8, Y9Y13 Output Disable Time HD to B1B8, Y9Y13 Output EnableOutput Disable Output Slew Rate B1B8, Y9Y13
2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0
0.05 0.05
0.40 0.40 120 120
0.05 0.05
0.40 0.40 120 120
V/ns
Figure 5 Figure 4 Figure 6 (Note 10)
ns
Capacitance
Symbol CIN CI/O (Note 11) Parameter Input Capacitance I/O Pin Capacitance Typ 3 5 Units pF pF VCC = 3.3V Conditions VCC = 0.0V (HD, DIR, A9A13, C14C17, PLHIN and HLHIN)
Note 11: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012
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