|
|
Part: 74LVXC4245QSCX
Category:
Description: 8-Bit Dual Supply Configurable Voltage Interface Transceiver With 3-STATE Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74LVXC4245QSCX datasheet File size : 110 kB
Request For quote: Find where to buy 74LVXC4245QSCX
Datasheet text preview:
74LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs
February 1994 Revised July 1999
74LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs
General Description
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for PCMCIA and other real time configurable I/O applications. The VCCA pin accepts a 5V supply level. The "A" Port is a dedicated 5V port. The VCCB pin accepts a 3V-to-5V supply level. The "B" Port is configured to track the VCCB supply level respectively. A 5V level on the VCC pin will configure the I/O pins at a 5V level and a 3V VCC will configure the I/O pins at a 3V level. This device will allow the VCCB voltage source pin and I/O pins on the "B" Port to float when OE is HIGH. This feature is necessary to buffer data to and from a PCMCIA socket that permits PCMCIA cards to be inserted and removed during normal operation.
Features
s Bidirectional interface between 5V and 3V-to-5V buses s Control inputs compatible with TTL level s Outputs source/sink up to 24 mA s Guaranteed simultaneous switching noise level and dynamic threshold performance s Implements patented EMI reduction circuitry s Flexible VCCB operating range s Allows B Port and VCCB to float simultaneously when OE is HIGH s Functionally compatible with the 74 series 245
Ordering Code:
Order Number 74LVXC4245WM 74LVXC4245QSC 74LVXC4245MTC Package Number M24B MQA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OE T/R A0A7 B0B7 Description Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS012009
www.fairchildsemi.com
74LVXC4245
Truth Table
Inputs OE L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Outputs T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH-Z State
Logic Diagram
www.fairchildsemi.com
2
74LVXC4245
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCCA,VCCB) DC Input Voltage (VI) @ OE, T/R DC Input/Output Voltage (VI/O) @ An @ Bn DC Input Diode Current (IIK) @ OE, T/R DC Output Diode Current (IOK) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) and Max Current Storage Temperature Range (TSTG) DC Latch-Up Source or Sink Current ±300 mA ±50 mA ±200 mA -65°C to +150°C ±50 mA ±20 mA ±50 mA -0.5V to VCCA +0.5V -0.5V to VCCB +0.5V -0.5V to +7.0V -0.5V to VCCA +0.5V
Recommended Operating Conditions (Note 2)
Supply Voltage VCCB Input Voltage (VI) @ OE, T/R Input/Output Voltage (VI/O) @An @Bn Free Air Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 30% to 70% of VCC VCC @ 3V, 4.5V, 5.5V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: The A Port unused pins (inputs and I/O's) must be held HIGH or LOW. They may not float.
VCCA
4.5V to 5.5V 2.7V to 5.5V 0V to VCCA 0V to VCCA 0V to VCCB -40°C to +85°C 8 ns/V
DC Electrical Characteristics
Symbol VIHA Parameter Minimum HIGH Level Input Voltage An OE T/R VIHB Bn VCCA (V) 4.5 4.5 5.5 4.5 4.5 4.5 VILA Maximum LOW Level Input Voltage An OE T/R VILB Bn 4.5 4.5 5.5 4.5 4.5 4.5 VOHA VOHB Minimum HIGH Level Output Voltage 4 .5 4 .5 4.5 4.5 4.5 4.5 4.5 4.5 VOLA VOLB Maximum LOW Level Output Voltage 4 .5 4 .5 4.5 4.5 4.5 4.5 4.5 IIN Maximum Input Leakage Current @ OE, T/R 5.5 5.5 3.6 5 .5 ±0.1 ±0.1 ±1.0 ±1.0 µA VCCB (V) 2 .7 3 .6 5 .5 2 .7 3 .6 5 .5 2 .7 3 .6 5 .5 2 .7 3 .6 5 .5 3.0 3.0 3 .0 3.0 3.0 2 .7 2 .7 4.5 3.0 3.0 3 .0 3.0 2 .7 2 .7 4.5 4.49 4.25 2.99 2.85 2.65 2.5 2.3 4.25 0.002 0.21 0.002 0.21 0.11 0.22 0.18 TA = +25°C Typ 2.0 2.0 2.0 2.0 2.0 3.85 0.8 0.8 0.8 0.8 0.8 1.65 4 .4 3.86 2.9 2.56 2.35 2 .3 2 .1 3.86 0.1 0.36 0.1 0.36 0.36 0.42 0.36 TA = -40°C to +85°C Guaranteed Limits 2.0 2.0 2.0 2.0 2.0 3.85 0.8 0.8 0.8 0.8 0.8 1.65 4.4 3.76 2.9 2.46 2.25 2.2 2.0 3.76 0.1 0.44 0.1 0.44 0.44 0.5 0.44 V V V V IOUT = -100 µA IOH = -24 mA IOUT = -100 µA IOH = -12 mA IOH = -24 mA IOH = -12 mA IOH = -24 mA IOH = -24 mA IOUT = 100 µA IOL = 24 mA IOUT = 100 µA IOL = 24 mA IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCCA, GND V VOUT 0.1V or VCC - 0.1V V Units Conditions VOUT 0.1V or VCC - 0.1V
3
www.fairchildsemi.com
74LVXC4245
DC Electrical Characteristics
Symbol IOZA Parameter Maximum 3-STATE Output Leakage @ A n IOZB ICC ICCA1 Maximum 3-STATE Output Leakage @ B n Maximum ICC/Input Quiescent VCCA Supply Current as B Port Floats ICCA2 Quiescent VCCA Supply Current 5.5 5.5 ICCB Quiescent VCCB Supply Current 5.5 5.5 VOLPA VOLPB VOLVA VOLVB VIHDA VIHDB VILDA VILDB Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5 .0 5.0 5.0 5.0 5 .0 5.0
Note 3: Worst case package.
(Continued)
TA = +25°C Typ ± 0.5 ± 0.5 ± 0.5 ± 0.5 1 .0 1.35 0.35 8 TA = -40°C to +85°C Guaranteed Limits ±5.0 ±5.0 ±5.0 ±5.0 1.5 0.5 80 µA µA mA mA µA VI = VIL, VIH, OE = VCCA VO = VCCA, GND VI = VIL, VIH, OE = VCCA VO = VCCB, GND VI = VCC - 2.1V VI = VCCB - 0.6V An = VCCA or GND Bn = Open, OE = VCCA T/R = VCCA, VCCB = Open An = VCCA or GND 3 .6 5 .5 8 8 80 80 µA µA Bn = VCCB or GND OE = GND, T/R = GND An = VCCA or GND 3 .6 5 .5 3 .3 5.0 3 .3 5 .0 3 .3 5 .0 3 .3 5 .0 3.3 5.0 3.3 5 .0 3 .3 5 .0 3.3 5 .0 5 8 1.5 1.5 0.8 1.5 - 1.2 - 1.2 - 0.8 - 1.2 2.0 2.0 2 .0 3.5 0.8 0.8 0 .8 1.5 50 80 V V V V V V V V Bn = VCCB or GND OE = GND, T/R = VCCA (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 5) (Note 3) (Note 5) (Note 3) (Note 5) (Note 3) (Note 5)
VCCA (V) 5.5 5.5 5.5 5.5 All Inputs Bn 5 .5 5.5 5.5
VCCB (V) 3.6 5 .5 3.6 5 .5 5.5 3 .6 Open
Units
Conditions
Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. Note 5: Max number of Data Inputs (n) switching. (n-1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.
www.fairchildsemi.com
4
74LVXC4245
AC Electrical Characteristics
CL = 50 pF VCCA = 4.5V to 5.5V Symbol Parameter Min tPHL tPLH tPHL tPLH tPZL tPZH tPZL tPZH tPHZ tPLZ tPHZ tPLZ tOSHL tOSLH Propagation Delay A to B Propagation Delay B to A Output Enable Time OE to B Output Enable Time OE to A Output Disable Time OE to B Output Disable Time OE to A Output to Output Skew (Note 8) Data to Output
Note 6: Typical values at VCCA = 5V, VCCB = 5V @25°C. Note 7: Typical values at VCCA = 5V, VCCB = 3.3V @25°C. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
CL = 50 pF VCCA = 4.5V to 5.5V VCCB = 2.7V to 3.6V TA = +25°C M in 1.0 1.0 1.0 1.0 1 .0 1 .0 1.0 1 .0 1 .0 1 .0 1 .0 1 .0 Typ (Note 7) 5.5 5.0 5.6 4.3 6.7 6.9 8.0 6.3 6.0 4.2 3.4 2.9 M ax 7.5 7.0 7.5 6.0 9 .0 9 .5 10.0 8 .0 9 .0 6 .5 5 .5 5 .0 TA = -40°C to +85°C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.0 7.5 8.0 6.5 10.0 10.0 11.0 8.5 9.5 7.0 6.0 5.5 Units
VCCB = 4.5V to 5.5V TA = +25°C Typ (Note 6) 1 .0 1 .0 1 .0 1 .0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.9 4.0 4.7 3.9 5 .6 5 .7 7 .4 6 .1 4 .8 3 .8 3 .4 2 .9 6 .5 5 .5 6 .5 5 .0 7.5 7.5 9.0 7.5 7.0 5.5 5.5 4.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 7.0 6.0 7.0 5.5 8.0 8.0 10.0 8.5 7.5 6.0 6.0 5.0 Max TA = -40°C to +85°C M in Max
ns ns ns
ns
ns
ns
1.0
1 .5
1.5
1.0
1.5
1.5
ns
Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (Note 9)
Note 9: CPD is measured at 10 MHz.
Parameter
Typ 4.5 10 AB BA 45 50
Units pF pF pF pF VCC = Open
Conditions VCCA = 5V, VCCB = 3.3V VCCA = 5V VCCB = 3.3V
Power Up Considerations
To insure the system does not experience unnecessary ICC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1): · Power up the control side of the device first. This is the VCCA. · OE should ramp with or ahead of VCCA. This will help guard against bus contention. · The Transmit/Receive control pin (T/R) should ramp with VCCA, this will ensure that the A Port data pins are configured as inputs. With VCCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations. · A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. The above steps will ensure that no bus contention or oscillations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type 74LVXC4245 VCCA 5V (power up 1st) VCCB 2.7V to 5.5V configurable T/R ramp with VCCA OE ramp with VCCA A Side I/O logic 0V or VCCA B Side I/O outputs Floatable Pin Allowed yes, VCCB and B I/O's w/ OE HIGH
Please reference Application Note AN-5001 for more detailed information on using Fairchild's LVX Low Voltage Dual Supply CMOS Translating Transceivers.
5
www.fairchildsemi.com
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
