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Details, datasheet, quote on part number:74LVXZ161284MTX
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Datasheet text preview:
74LVXZ161284 · 74LVXZ161284B Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection
May 2002 Revised April 2003
74LVXZ161284 · 74LVXZ161284B Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection
General Description
These transceivers contain eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The devices support the IEEE 1284 standard and are intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (VCC-Cable) that allows these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, the C inputs and the B and Y outputs on the cable side contain internal pull-up resistors connected to the VCC-Cable supply to provide proper input termination and pull-ups for open drain output mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1A8/B1B8 transceiver pins. The devices also have an added power-up protection feature which forces the Y outputs (Y9 - Y13) to a high state after power-on until one of the associated inputs (A9 - A13) goes HIGH. When an associated input (A9 - A13) goes HIGH, all Y outputs (Y9 - Y13) are activated. The 74LVXZ161284B device provides increased noise tolerance for stable power-on circuit logic states.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s Translation capability allows outputs on the cable side to interface with 5V signals s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s C inputs and B, Y outputs on cable side have internal 1.4 k pull-up resistors s Flow-through pin configuration allows easy interface between the "Peripheral and Host" s Replaces the function of two (2) 74ACT1284 devices s Power-up protection prevents errors when the printer is powered on but no valid signal is at the input pins (A9 - A13).
Ordering Code
Order Number 74LVXZ161284MEA 74LVXZ161284MEX 74LVXZ161284MTD 74LVXZ161284MTX 74LVXZ161284BMT 74LVXZ161284BTX Package Number MS48A MS48A MTD48 MTD48 MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [RAIL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
© 2003 Fairchild Semiconductor Corporation
DS500729
www.fairchildsemi.com
74LVXZ161284 · 74LVXZ161284B
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names HD DIR A1A8 B1B8 A9A13 Y9Y13 A14A17 C14C17 PLHIN PLH HLHIN HLH Description High Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output
Truth Table
Inputs DI R L HD L B1B8 Data to A1A8, and A9A13 Data to Y9Y13 (Note 1) C14C17 Data to A14A17 PLH Open Drain Mode L H B1B8 Data to A1A8, and A9A13 Data to Y9Y13 C14C17 Data to A14A17 H L A1A8 Data to B1B8 (Note 2) A9A13 Data to Y9Y13 (Note 1) C14C17 Data to A14A17 PLH Open Drain Mode H H A1A8 Data to B1B8 A9A13 Data to Y9Y13 C14C17 Data to A14A17
Note 1: Y9Y13 Open Drain Outputs with 1.4 k pull-ups Note 2: B1B8 Open Drain Outputs with 1.4 k pull-ups
Outputs
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74LVXZ161284 · 74LVXZ161284B
Logic Diagrams
Input Detection Circuit
FIGURE 1. Input Detection Circuit Timing
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74LVXZ161284 · 74LVXZ161284B
With 74LVXZ161284B any of the A9 - A13 inputs may transition HIGH prior to VCC and VCC-Cable becoming stable. In this case it is critical that VCC-Cable does not ramp earlier than VCC. VCC and VCC-Cable ramping concurrently will result in valid operation of this device. Concurrent ramping is defined as VCC and VCC-Cable having less than a 500 µs delta between them. FIGURE 2. 74LVXZ161284B Adds Tolerance to Power-On Noise www.fairchildsemi.com
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74LVXZ161284 · 74LVXZ161284B
Absolute Maximum Ratings(Note 3)
Supply Voltage VC C VCC--Cable VCC--Cable Must Be VCC Input Voltage (VI)--(Note 4) A1A13, PLHIN , DIR, HD B1B8, C14C17, HLHIN B1B8, C14C17, HLHIN Output Voltage (VO) A1A8, A14A17, HLH B1B8, Y9Y13, PLH B1B8, Y9Y13, PLH DC Output Current (IO) A1A8, HLH B1B8, Y9Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK)--(Note 4) DIR, HD, A9A13, PLH, HLH, C14C17 Output Diode Current (IOK) A1A8, A14A17, HLH B1B8, Y9Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD Human Body Model Machine Model Charged Device Model 4000V 200V 2000V
Recommended Operating Conditions
Supply Voltage VC C VCC--Cable DC Input Voltage (VI) Open Drain Voltage (VO) Operating Temperature (TA) 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V
-0.5V to +4.6V -0.5V to +7.0V
-0.5V to VCC + 0.5V -0.5V to +5.5V (DC) -2.0V to +7.0V*
*40 ns Transient
-40°C to +85°C
-0.5V to VCC +0.5V -0.5V to +5.5V (DC) -2.0V to +7.0V*
*40 ns Transient
±25 mA ±50 mA
84 mA
-50 mA -20 mA ±50 mA -50 mA ±200 mA -65°C to +150°C
Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Fairchild does not recommend operation outside the databook specifications. Note 4: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VT Minimum Input Hysteresis VOH Minimum HIGH Level Output Voltage Bn, Yn Bn, Yn PLH An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, HLH 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3 .3 3.3 3.3 3 .0 3.0 3.0 3.0 3 .15 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 5.0 5.0 5.0 3.0 3.0 3.0 4.5 3.15 2.0 2.3 2.6 0.8 0.8 1.6 0.4 0.8 0.2 2.8 2.4 2.0 2.23 3.1 2.0 2.3 2.6 0.8 0.8 1.6 0.4 0.8 0.2 2.8 2.4 2.0 2.23 3.1 V V VT+ VT- VT+ VT- VT+ VT- IOH = -50 µA IOH = -4 mA IOH = -14 mA IOH = -14 mA IOH = -500 µA V V Parameter V CC (V) 3.0 VCC--Cable (V) 3.0 TA = 0°C to +70°C -1.2 TA = -40°C to +85°C -1.2 Units V Conditions Ii = -18 mA
Guaranteed Limits
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