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Part: 74VCXH16373MTDX
Category:
Description: Low Voltage 16-Bit Transparent Latch With Bushold
Company: Fairchild Semiconductor
Datasheet: Download 74VCXH16373MTDX datasheet File size : 110 kB
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74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold
January 2000 Revised February 2002
74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The VCXH16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The VCXH16373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16373 is designed for low voltage (1.4V to 3.6V) VCC applications with output compatibility up to 3.6V. The 74VCXH16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD (In to On) 3.0 ns max for 3.0V to 3.6V VCC s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Ordering Code:
Order Number 74VCXH16373GX (Note 1) 74VCXH16373MTD (Note 2) Package Number BGA54A (Preliminary) MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500229
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74VCXH16373
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names OEn LEn I0I15 O0O15 NC Description Output Enable Input (Active LOW) Latch Enable Input Bushold Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O 10 O 12 O 14 O 15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VC C G ND G ND G ND VC C NC OE2 4 LE1 NC VCC GND GND GND VCC NC LE2 5 NC I1 I3 I5 I7 I9 I11 I 13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs LE1 Pin Assignment for FBGA X H H L OE1 H L L L Inputs LE2 X H H L (Top Thru View) OE2 H L L L I8I15 X L H X I0I7 X L H X Outputs O0O7 Z L H O0 Outputs O8O15 Z L H O0
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, control inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable
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74VCXH16373
Functional Description
The 74VCXH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VCXH16373
Absolute Maximum Ratings(Note 3)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 4) DC Input Diode Current (IIK) VI VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (I CC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to +4.6V -0.5V to VCC +0.5V -50 mA -50 mA +50 mA ±50 mA ±100 mA -65°C to +150°C
Recommended Operating Conditions (Note 5)
Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in "OFF" State Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V VCC = 1.4V to 1.6V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused inputs must be held HIGH or LOW.
1.4V to 3.6V
-0.3V to +3.6V
0V to VCC 0.0V to 3.6V
±24 mA ±18 mA ±6 mA ±2 mA -40°C to +85°C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VIL LOW Level Input Voltage 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VOH HIGH Level Output Voltage IOH = -100 µA IOH = -12 mA IOH = -18 mA IOH = -24 mA IOH = -100 µA IOH = -6 mA IOH = -12 mA IOH = -18 mA IOH = -100 µA IOH = -6 mA IOH = -100 µA IOH = -2 mA 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2 .0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 V Min 2.0 1 .6 0 .65 x V CC 0 . 6 5 x V CC 0.8 0.7 0.35 x VCC 0.35 x VCC V V Max Units
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74VCXH16373
DC Electrical Characteristics
Symbol VOL Parameter LOW Level Output Voltage
(Continued)
VCC (V) IOL = 100 µA IOL = 12 mA IOL = 18 mA IOL = 24 mA IOL = 100 µA IOL = 12 mA IOL = 18 mA IOL = 100 µA IOL = 6 mA IOL = 100 µA IOL = 2 mA 2.7- 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 1.4 - 3.6 1.4 - 3.6 3.0 3.0 2.3 2.3 1.65 1.65 3.6 3.6 2.7 2.7 1.95 1.95 2.73.6 0 1.4 - 3.6 1.4 - 3.6 2.7 - 3.6 75 - 75 45 - 45 25 - 25 450 -450 300 -300 200 -200 ±10 10 20 ±20 750 µA µA µA µA µA µA 0 .2 0 .4 0 .4 0.55 0.2 0 .4 0 .6 0 .2 0.3 0 .2 0.35 ±5.0 ±5.0 µA µA V
Conditions
Min
M ax
Units
II II(HOLD)
Input Leakage Current Bushold Input Minimum Drive Hold Current
Control Pins Data Pins
0 VI 3.6V VI = V CC or GND VIN = 0.8V VIN = 2.0V VIN = 0.7V VIN = 1.6V VIN = 0.57V VIN = 1.07V
II(OD)
Bushold Input Over-Drive Current to Change State
(Note 6) (Note 7) (Note 6) (Note 7) (Note 6) (Note 7)
IOZ IOFF ICC ICC
3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input
0 VO 3.6V VI = V IH or VIL 0 (VO) 3.6V VI = V CC or GND VCC (VO) 3.6V (Note 8) VIH = VCC - 0.6V
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: Outputs disabled or 3-STATE only.
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