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Details, datasheet, quote on part number:74VHC161284
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Datasheet text preview:
74VHC161284 IEEE 1284 Transceiver
February 1998 Revised November 2000
74VHC161284 IEEE 1284 Transceiver
General Description
The VHC161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA). The pull-up and pulldown series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCC supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard LOW-drive CMOS outputs. The DIR input controls data flow on the A1A8/B1B8 transceiver pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s Replaces the function of two (2) 74ACT1284 devices s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interface between the Peripheral and Host
Ordering Code:
Ordering Number Package Number 74VHC161284MEA 74VHC161284MTD MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS500098
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74VHC161284
Pin Descriptions
Pin Names HD DIR A1A8 B1B8 A9A13 Y9Y13 A14A17 C14C17 PLHIN PLH HLHIN HLH Description HIGH Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output
Truth Table
Inputs DIR L HD L Outputs B1B8 Data to A1A8, and A9A13 Data to Y9Y13 (Note 1) C14C17 Data to A14A17 PLH Open Drain Mode L H B1B 8 Data to A1A8, and A9A13 Data to Y9Y13 C14C17 Data to A14A17 H L A1A8 Data to B1B8 (Note 2) A9A13 Data to Y9Y13 (Note 1) C14C17 Data to A14A17 PLH Open Drain Mode H H A1A8 Data to B1B8 A9A13 Data to Y9Y13 C14C17 Data to A14A17
Note 1: Y9Y13 Open Drain Outputs Note 2: B1B8 Open Drain Outputs
Logic Diagram
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74VHC161284
Absolute Maximum Ratings(Note 3)
Supply Voltage VCC Input Voltage (VI) (Note 4) A1A 13, PLHIN, DIR, HD B1B8, C14C17, HLHIN B1B8, C14C17, HLHIN Output Voltage (VO) A1A8, A14A17, HLH B1B 8, Y9Y13, PLH B1B 8, Y9Y13, PLH DC Output Current (IO) A1A8, HLH B1B8, Y9Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK) (Note 4) DIR, HD, A9A13, PLH, HLH, C14C17 Output Diode Current (IOK) A1A8, A14A17, HLH B1B8, Y9Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD (HBM) Last Passing Voltage 2000V
Recommended Operating Conditions
Supply Voltage VC C DC Input Voltage (VI) Open Drain Voltage (VO) Operating Temperature (TA) 4.5V to 5.5V 0V to VCC 0V to 5.5V
-0.5V to + 7.0V -0.5V to VCC + 0.5V -0.5V to + 5.5V (DC) -2.0V to + 7.0V *
*40 ns Transient
-40°C to + 85°C
-0.5V to VCC + 0.5V -0.5V to + 5.5V (DC) -2.0V to + 7.0V*
*40 ns Transient
±25 mA ±50 mA
84 mA
-50 mA
-20 mA ±50 mA -50 mA ±200 mA -65°C to + 150°C
Note 3: Absolute Maximum continuos ratings are those values beyond which damage to the device may occur. Exposure to these indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage An, PLHIN, DIR, HD Bn Cn HLHIN VIL Maximum LOW Level Input Voltage An, PLHIN, DIR, HD Bn Cn HLHIN VT Minimum Input Hysteresis An, PLHIN, DIR, HD Bn Cn HLHIN VOH Minimum HIGH Level Output Voltage An, HLH Bn, Yn PLH Parameter VCC (V) 3.0 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 5.0 5.0 4.5 4.5 4.5 4.5 TA = -40°C to +85°C Guaranteed Limits -1.2 0 .7 V CC 2 .0 2 .3 2 .6 0 .3 V CC 0 .8 0 .8 1 .6 0 .4 0 .4 0 .8 0 .3 4.4 3 .8 3.73 4.45 V V VT + VT- VT+ VT- VT + VT- VT + VT- IOH = -50 µA IOH = -8 mA IOH = -14 mA IOH = -500 µA V V V II = -18 mA Units Conditions
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74VHC161284
DC Electrical Characteristics
Symbol VOL Parameter Maximum LOW Level Output Voltage
(Continued)
VCC (V) 4 .5 4.5 4.5 4 .5 5.0 5.0 5.0 5.0 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 0 .0 0.0 0.0 5.5 TA = -40°C to +85°C Guaranteed Limits 0.1 0 .44 0 .77 0 .7 55 35 1650 1150 1 .0 100 - 1.0 - 5.0 20 100 - 20 - 5.0 100 100 250 70 µA µA mA µA µA mA µA µA µA mA VO = 5.5V VI = 5.5V (Note 7) VI = VCC or GND VI = 5.5V VI = 5.5V VI = 0.0V VI = 0.0V VO = 5.5V VO = 5.5V VO = 0.0V V IOL = 50 µA IOL = 8 mA IOL = 14 mA IOL = 84 mA (Note 5)(Note 6) (Note 5)(Note 6)
Units
Conditions
An, HLH Bn, Yn P LH
RD RP IIH IIL IOZH IOZL IOFF IOFF IOFF - ICC ICC
Maximum Output Impedance Minimum Output Impedance Maximum Pull-Up Resistance Minimum Pull-Up Resistance Maximum Input Current in HIGH State Maximum Input Current in LOW State Maximum Output Disable Current (HIGH) Maximum Output Disable Current (LOW) Power Down Output Leakage Power Down Input Leakage Power Down Leakage to VCC Maximum Supply Current
B1B8, Y9Y13 B1B8, Y9Y13 B1B8, Y9Y13, C14C17 B1B8, Y9Y13, C14C17 A9A13, PLHIN, HD, DIR, HLHIN C14C17 A9A13, PLHIN, HD, DIR, HLHIN C14C17 A1--A8 B1B8 A1--A8 B1B8 B1B8, Y9Y13, PLH C14C17, HLHIN
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH). Note 6: This parameter is guaranteed but not tested, characterized only. Note 7: Power-down leakage to VCC is tested by simultaneously forcing all pins on the cable-side (B1B8, Y9Y13, PLH, C14C17 and HLHIN to 5.5V and m easuring the resulting ICC.
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74VHC161284
AC Electrical Characteristics
TA = -40°C to +85°C Symbol Parameter VCC = 4.5V - 5.5V Min tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tSKEW tPHL tPLH tPHL tPLH tPHZ tPLZ tPZH tPZL tPHZ tPLZ tpEN tpDis tpEntpDis tSLEW tPLH tPHL tr, tf tRISE and tFALL B1B8, Y9Y13 (Note 8)
Note 8: Open Drain Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type. (i) A1A8 to B1B8, A9Y13 to Y9Y13 (ii) B1B8 to A1A8 (iii) C14C17 to A14A17 Note 10: This parameter is guaranteed but not tested, characterized only.
Units
Figure Number Figure 1 Figure 2 Figure 3 Figure 3 Figure 1 Figure 2 Figure 3 Figure 3 (Note 9) Figure 1 Figure 2 Figure 3 Figure 3 Figure 7 Figure 8 Figure 9 Figure 2 Figure 2
M ax 30.0 30.0 30.0 30.0 30.0 30.0 30.0 30.0 6.0 30.0 30.0 30.0 30.0 18.0 18.0 25.0 25.0 25.0 25.0 28.0 28.0 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 5 Figure 4 Figure 6 (Note 10)
A1A8 to B1B8 A1A8 to B1B8 B1B8 to A1A8 B1B8 to A1A8 A9A13 to Y9Y13 A9A13 to Y9Y13 C14C17 to A14A17 C14C17 to A14A17 LH-LH or HL-HL PLHIN to PLH PLHIN to PLH HLHIN to HLH HLHIN to HLH Output Disable Time DIR to A1A8 Output Enable Time DIR to A1A8 Output Disable Time DIR to B1B8 Output Enable Time HD to B1B8, Y9Y13 Output Disable Time HD to B1B8, Y9Y13 Output Enable-Output Disable Output Slew Rate B1B8, Y9Y13
2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0
0.05 0.05
0.40 0.40 120 120
V/ns ns
Capacitance (Note 11)
Symbol CIN CI/O Parameter Input Capacitance I/O Pin Capacitance Typ 5 12 Units pF pF VCC = 3.3V Conditions VCC = 0.0V (HD, DIR, A9--A13, C14--C17, PLHIN and HLHIN)
Note 11: Capacitance is measured at frequency = 1 MHz.
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