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Details, datasheet, quote on part number:74VHC374N
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Datasheet text preview:
74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1992 Revised April 1999
74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHC374 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a HIGH impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: tPD = 5.4 ns (typ) at VCC = 5V s High noise immunity: VNIH = VNIL = 28% VCC (Min) s Power down protection is provided on all inputs s Low power dissipation: ICC = 4 µA (Max) @ TA = 25°C s Pin and function compatible with 74HC374
Ordering Code:
Order Number 74VHC374M 74VHC374SJ 74VHC374MTC 74VHC374N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names D0 D7 CP OE O0O7 Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS011538.prf
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74VHC374
Functional Description
The VHC374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Truth Table
Inputs Dn H L X CP Outputs OE L L H On H L Z
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC374
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260°C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA ±20 mA ±25 mA ±75 mA -65°C to +150°C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V 0 ns/V 100 ns/V 0 ns/V 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC -40°C to +85°C
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage V CC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 ±0.1 4.0 ±1.0 40.0 µA µA 5.5 1 .9 2.9 4 .4 2 .58 3 .94 0 .0 0.0 0 .0 0.1 0.1 0.1 0.36 0.36 ±0.25 2.0 3.0 4.5 TA = 25°C Min 1 .50 0.7 VCC 0.50 0.3 VCC 1 .9 2.9 4 .4 2 .48 3 .80 0 .1 0.1 0 .1 0 .44 0 .44 ±2.5 V µA IOL = 4 mA IOL = 8 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5V or GND VIN = VCC or GND V V VIN = VIH or VIL IOH = -4 mA IOH = -8 mA IOL = 50 µA V Typ Max TA = -40°C to +85°C M in 1 .50 0.7 VCC 0 .50 0.3 VCC Max Units V V VIN = VIH or VIL IOH = -50 µA Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA = 25°C Typ 0.6 -0.6 Limits 0.9 - 0.9 3.5 1 .5 Units V V V V Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
Note 3: Parameter guaranteed by design.
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74VHC374
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time (CP to On) 5.0 ± 0.5 tPZL tPZH 3-STATE Output Enable Time 5.0 ± 0.5 tPLZ tPHZ tOSLH tOSHL fMAX 3-STATE Output Disable Time Output to Output Skew 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 Maximum Clock Frequency 3.3 ± 0.3 5.0 ± 0.5 CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance
Note 4: Parameter guaranteed by design. tOSLH = |tPLH max - t PLH min|; tOSHL = |tPHL max - tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) = 20 + 12n.
V CC (V) 3.3 ± 0.3
TA = 25°C Min Typ 8 .1 10.6 5 .4 6 .9 7 .1 9.6 5 .1 6.6 10.2 6 .1 Max 12.7 16.2 8.1 10.1 11.0 14.5 7.6 9.6 14.0 8.8 1.5 1.0 80 55 130 85 130 85 185 120 4 6 32 10
TA = -40°C to +85°C M in 1.0 1 .0 1 .0 1 .0 1.0 1 .0 1 .0 1.0 1 .0 1 .0 Max 15.0 18.5 9.5 11.5 13.0 16.5 9.0 11.0 16.0 10.0 1.5 1.0 70 50 110 75 10
Units ns ns ns ns ns ns
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF RL = 1 k CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF RL = 1 k (Note 4) CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF VCC = Open VCC = 5.0V (Note 5)
3.3 ± 0.3
MHz
pF pF pF
AC Operating Requirements
Symbol tW(H) tW(L) tS tH Minimum Set-Up Time Minimum Hold Time Parameter Minimum Pulse Width (CP) VCC (V) 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 TA = 25°C Min 5.0 5.0 4.5 3.0 2.0 2.0 Typ Max TA = -40°C to +85°C M in 5.5 5.0 4.5 3.0 2.0 2.0 ns Max Units ns ns
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74VHC374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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