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Details, datasheet, quote on part number:FDP11N50
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Datasheet text preview:
FDP11N50
July 2003
FDP11N50
11A, 500V, 0.725 Ohm, N-Channel SMPS Power MOSFET
Applications
Switch Mode Power Supplies(SMPS), such as · PFC Boost · Two-S witch Forward Converter · Single Switch Forward Converter · Flyback Converter · Buck Converter · High Speed Switching
Features
· Low Gate Charge Requirement Qg results in Simple Drive
· Improved Gate, Avalanche and High Reapplied dv/dt Ruggedness · Reduced r DS(ON) · Reduced Miller Capacitance and Low Input Capacitance · Improved Switching Speed with Low EMI · 175°C Rated Junction Temperature
Packages
JEDEC TO-220AB
SOURC E DRAIN GATE DRAIN (FLANGE)
Symbol
D
G S
Absolute Maximum Ratings TC = 25°C unless otherwise noted
S ymbol VD SS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC = 25oC, VGS = 10V) Continuous (TC = 100 C, VGS = 10V) Pulsed PD TJ, TST G Power dissipation Derate above 25oC Operating and Storage Temperature Soldering Temperature for 10 seconds Mounting Torque, 8-32 or M3 Screw
o
Ratings 500 ±30 11 7.8 44 250 1.6 - 55 to 175 300 (1.6mm from case) 10ibf*in (1.1N*m)
Units V V A A A W W/oC
o o
C C
Thermal Characteristics
R JC R CS R JA Thermal Resistance Junction to Case Thermal Resistance Case to Sink, Flat, Greased Surface Thermal Resistance Junction to Ambient 0.60 0.50 TYP 62
o o o
C/W C/W C/W
©2003 F a irc hild Semiconductor Corporation
F DP1 1 N50 Rev. A1
July 2003
FDP11N50
Package Marking and Ordering Information
Device Marking FDP11N50 Device FDP11N50 Package TO-220AB Reel Size Tube Tape Width Quantity 50
Electrical Characteristics TJ = 25°C (unless otherwise noted)
Symbol Parameter Test Conditions Min Typ Max Units
Statics
B V DS S BVD SS/TJ rD S ( O N ) VGS(th) ID SS IGSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 500 2.0 0.53 0.615 0.725 4.0 25 250 ±100 V V/°C V µA nA Refer ence to 25°C, Breakdown Voltage Temp. Coefficient ID = 1mA Drain to Source On-Resistance Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current VGS = 10V, ID = 5.5A VD S = VGS, ID = 250µA VD S = 500V VGS = 0V VGS = ±30V TC = 25oC TC =150oC
Dynamics
gfs Qg(TOT) Qg s Qg d t d ( O N) tr t d ( O FF) tf CISS CO S S CR S S Forward Transconductance Total Gate Charge at 10V Gate to Source Gate Charge Gate to Drain "Miller" Charge Tur n- On Delay Time Rise Time Tur n- Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance VD S = 50V, ID = 5.5A VGS = 10V, VD S = 400V, ID = 11A VD D = 250V, ID = 11A RG = 9.1, RD = 22.7 VD S = 25V, VGS = 0V, f = 1MHz 6 17.0 5.0 6.0 10 21 26 21 1020 127 7.4 20.5 6.0 7.0 S nC nC nC ns ns ns ns pF pF pF
Avalanche Characteristics
E AS IAR Single Pulse Avalanche Energy2 Avalanche Current 605 11 mJ A
Drain-Source Diode Characteristics
IS ISM V SD t rr Q RR
Notes:
1: Repetitive rating; pulse width limited by minimum junction temperature 2: Starting TJ = 25°C, L = 10 mH, IAS = 11A
Continuous Source Current (Body Diode) Pulsed Source (Body Diode) Current1
MOSFE T symbol showing the integral reverse p-n junction diode. G ISD = 11A
D
0.89 418 3.7
11 44 1.2 543 4.8
A A V ns µC
S
Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge
-
ISD =11A, dISD /dt = 100A/µs ISD = 11A, dISD/dt = 100A/µs
©2003 Fairchild Semiconductor Corporation
F DP1 1 N50 Rev. A1
July 2003
FDP11N50
Typical Characteristics
ID, DRAIN TO SOURCE CURRENT (A)
50
VGS DESCENDING 10V 10 6.5V 6V 5.5V 5V 4.5V 1
I D, DRAIN TO SOURCE CURRENT (A)
TJ = 25oC
30
TJ = 175o C VGS DESCENDING 10V 5.5V 10 5V 4.5V 4V
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.1 0.1 1 10 100
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1 1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. Output Characteristics
NORMALIZED DRAIN TO SOURCE ON RESISTANCE 20
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 100V
Figure 2. Output Characteristics
3.0
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
2.5
ID , DRAIN CURRENT (A)
15
2.0
10
TJ = 175oC TJ = 25oC
1.5
1.0
5
0.5
VGS = 10V, ID = 5.5A
0 3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 -50
-25
0
25
50
75
100
125
150
175
VG S , GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (o C)
Figure 3. Transfer Characteristics
Figure 4. Normalized Drain To Source On Resistance vs Junction Temperatrue
15
2000
VGS , GATE TO SOURCE VOLTAGE (V)
1000 CISS
ID = 11A 100V 250V 10 400V
C, CAPACITANCE (pF)
100 COSS
10 CRSS VGS = 0V, f = 1MHz 1 1 10 100
5
0 0
5
10
15
20
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
Qg , GATE CHARGE (nC)
Figure 5. Capacitance vs Drain To Source Voltage
Figure 6. Gate Charge Waveforms For Constant Gate Current
©2003 Fairchild Semiconductor Corporation
F DP1 1 N50 Rev. A1
July 2003
FDP11N50
Typical Characteristics (Continued)
I SD , SOURCE TO DRAIN CURRENT (A)
25 100 TC = 25oC 10µs 20
ID, DRAIN CURRENT (A)
10 100µs
15
10 TJ = 175oC 5 TJ = 25oC
1
OPERATION IN THIS AREA LIMITED BY RDS (ON)
1ms 10ms DC
0 0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.1 1
10
100
1000
VSD , SOURCE TO DRAIN VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Source to Drain Diode Forward Voltage
12
Figure 8. Maximum Safe Operating Area
10
ID, DRAIN CURRENT (A)
8
6
4
2
0 25
50
75
100
125
150
175
TC, CASE TEMPERATURE (°C)
Figure 9. Maximum Drain Current vs Case Temperature
Z JC , NOR MALIZED THERMAL RESPONSE
1.0
0.50
0.20
0.1
t1 PD t2 DUTY FACTOR, D = t1 / t2 PEAK TJ = (PD X ZJC X RJC) + TC SINGLE PULSE
10-4 10-3 10-2 10-1 100
0.10 0.05 0.02 0.01
0.01 10 -5
t1 , RECTANGULAR PULSE DURATION (s)
Figure 10. Normalized Transient Thermal Impedance, Junction to Case
©2003 Fairchild Semiconductor Corporation
F DP1 1 N50 Rev. A1
July 2003
FDP11N50
Test Circuits and Waveforms
VDS tP L IA S VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG -
BVDSS
VDS VDD
+
VD D
IAS 0.01
0 tAV
Figure 11. Unclamped Energy Test Circuit
Figure 12. Unclamped Energy Waveforms
VDS RL
VDD
Qg(TOT) VD S
VGS = 10V
VGS
+
VD D DUT Ig(REF) 0
VGS VGS = 1V Qg(TH) Qgs Ig(REF ) 0 Qg d
Figure 13. Gate Charge Test Circuit
Figure 14. Gate Charge Waveforms
VDS
t ON td (ON) RL VDS 90% tr
tOFF td(OFF ) tf 90%
VGS
+
VD D DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 15. Switching Time Test Circuit
Figure 16. Switching Time Waveform
©2003 Fairchild Semiconductor Corporation
F DP1 1 N50 Rev. A1
July 2003
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