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Details, datasheet, quote on part number:FQA13N80
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Datasheet text preview:
FQA13N80
March 2001
QFET
FQA13N80
800V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies.
TM
Features
· · · · · · 12.6A, 800V, RDS(on) = 0.75 @VGS = 10 V Low gate charge ( typical 68 nC) Low Crss ( typical 30 pF) Fast switching 100% avalanche tested Improved dv/dt capability
D
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G! G DS
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TO-3P
FQA Series
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S
Absolute Maximum Ratings
Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL
TC = 25°C unless otherwise noted
Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed
(Note 1)
F Q A13N80 800 12.6 8. 0 50.4 ± 30
(Note 2) (Note 1) (Note 1) (Note 3)
Units V A A A V mJ A mJ V/ns W W/°C °C °C
Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C)
1100 12.6 30 4. 0 300 2.38 -55 to +150 300
- Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
Thermal Characteristics
Symbol RJ C RC S RJ A P arameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case-to-Sink Thermal Resistance, Junction-to-Ambient Typ -0. 24 -M ax 0. 42 -40 Units °C/W °C/W °C/W
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
FQA13N80
Electrical Characteristics
Symbol P a r a m e te r
TC = 25°C unless otherwise noted
Test Conditions
Min
Typ
Ma x
Units
Off Characteristics
BVDSS BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 800 V, VGS = 0 V VDS = 640 V, TC = 125°C VGS = 30 V, VDS = 0 V VGS = -30 V, VDS = 0 V 800 ------0.95 ------10 100 100 -100 V V/°C µA µA nA nA
On Characteristics
VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA VGS = 10 V, ID = 6.3 A VDS = 50 V, ID = 6.3 A
(Note 4)
3.0 ---
-0.58 13
5. 0 0.75 --
V S
Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---270 0 275 30 35 00 360 39 pF pF pF
Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 640 V, ID = 12.6 A, VGS = 10 V
(Note 4, 5)
VDD = 400 V, ID = 12.6 A, RG = 25
(Note 4, 5)
--------
60 150 155 110 68 15 32
130 310 320 230 88 ---
ns ns ns ns nC nC nC
Drain-Source Diode Characteristics and Maximum Ratings
IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 12.6 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 12.6 A, dIF / dt = 100 A/µs
(Note 4)
------
---850 11.3
12.6 50.4 1. 4 ---
A A V ns µC
Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 13mH, IAS = 12.6A, VDD = 50V, RG = 25 , Starting TJ = 25°C 3. ISD 12.6A, di/dt 200A/µs, VDD BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
FQA13N80
Typical Characteristics
10
1
VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V Top :
10
1
ID, Drain Current [A]
ID, Drain Current [A]
150 C
o
10
0
10
0
25 C -55 C
Notes : 1. VDS = 50V 2. 250 s Pulse Test
o
o
Notes : 1. 250 s Pulse Test 2. TC = 25
10
-1
10
-1
10
0
10
1
10
-1
2
4
6
8
10
VDS, Drain-Source Voltage [V]
VGS, Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
1.8
1.5
RDS(ON) [ ], Drain-Source On-Resistance
1.2
VGS = 20V
0.9
IDR, Reverse Drain Current [A]
VGS = 10V
10
1
10
0
150
25
Notes : 1. VGS = 0V 2. 250 s Pulse Test
0.6
Note : TJ = 25
0.3
0
5
10
15
20
25
30
35
40
45
10
-1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature
5000 4500 4000 3500
Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd
12
VDS = 160V
10
VDS = 400V VDS = 640V
VGS, Gate-Source Voltage [V]
Ciss
8
Capacitance [pF]
3000 2500 2000 1500 1000 500 0 -1 10
Coss
Notes : 1. VGS = 0 V 2. f = 1 MHz
6
4
Crss
2
Note : ID = 12.6 A
0 10
0
10
1
0
10
20
30
40
50
60
70
80
VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
FQA13N80
Typical Characteristics
(Continued)
1.2
3.0
2.5
BV DSS , (Normalized) Drain-Source Breakdown Voltage
RDS(ON) , (Normalized) Drain-Source On-Resistance
1.1
2.0
1.0
1.5
1.0
Notes : 1. VGS = 10 V 2. ID = 6.3 A
0.9
Notes : 1. VGS = 0 V 2. ID = 250 A
0.5
0.8 -100
-50
0
50
100
o
150
200
0.0 -100
-50
0
50
100
o
150
200
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation vs Temperature
Figure 8. On-Resistance Variation vs Temperature
14
10
2
Operation in This Area is Limited by R DS(on)
12
100 s
10 s
10
ID, Drain Current [A]
10
ID, Drain Current [A]
1
1 ms 10 ms DC
8 6 4 2 0 25
10
0
10
-1
Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse
o o
10
-2
10
0
10
1
10
2
10
3
50
75
100
125
150
VDS, Drain-Source Voltage [V]
TC, Case Temperature []
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current vs Case Temperature
(t), T h e rm a l R e s p o n s e
D = 0 .5
10
-1
0 .2 0 .1 0 .0 5 0 .0 2
N o te s : 1 . Z JC( t) = 0 . 4 2 /W M a x . 2 . D u t y F a c to r, D = t1/t 2 3 . T JM - T C = P D M * Z JC ( t)
P DM
s in g le p u ls e
JC
Z
10
-2
0 .0 1
t1
t2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u l s e D u r a t i o n [s e c ]
Figure 11. Transient Thermal Response Curve
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
FQA13N80
Gate Charge Test Circuit & Waveform
50K 12 V 200nF 300 nF
Same Type as DUT VDS
VGS 10V Qgs Qg
VGS
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS RG VGS
RL VDD
VDS
90%
10V
DUT
VGS
10%
td(on) t on
tr
td(off ) t off
tf
Unclamped Inductive Switching Test Circuit & Waveforms
L VDS ID RG 10V
tp
BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD ID (t) VDD
tp
DUT
VDS (t) Time
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
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