Details, datasheet, quote on part number: FQU7N20L
PartFQU7N20L
CategoryDiscrete => Transistors => FETs (Field Effect Transistors) => DMOS (Double-diffused MOS) => Logic Level
TitleLogic Level
Description200V N-channel Logic Level QFET
CompanyFairchild Semiconductor
DatasheetDownload FQU7N20L datasheet
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Features, Applications

These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation modes. These devices are well suited for high efficiency switching DC/DC converters, switch mode power supplies, and motor control.

Features

5.5A, 200V, RDS(on) = 0.75 @VGS 10 V Low gate charge ( typical 6.8 nC) Low Crss ( typical 8.5 pF) Fast switching 100% avalanche tested Improved dv/dt capability Low level gate drive requirement allowing direct operation from logic drivers

Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current - Continuous (TC = 100C) Drain Current - Pulsed

Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA 25C) * Power Dissipation (TC = 25C)

- Derate above 25C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

Symbol RJC RJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient * Thermal Resistance, Junction-to-Ambient Typ ---Max 50 110 Units C/W

* When mounted on the minimum pad size recommended (PCB Mount)

BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 250 A, Referenced to 25C VDS 200 V, VGS 0 V VDS = 125C VGS 20 V, VDS 0 V VGS -20 V, VDS V/C A nA

VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, 250 A VGS 2.75 A VGS 2.75 A VDS 2.75 A

Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS 25 V, VGS = 1.0 MHz pF

td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS 6.5 A, VGS 5 V

IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS 5.5 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS 6.5 A, dIF = 100 A/s

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature = 3.6mH, IAS = 5.5A, VDD 25 , Starting 25C 3. ISD 6.5A, di/dt 300A/s, VDD BVDSS, Starting 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature



Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature


 

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