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Details, datasheet, quote on part number:GTLP10B320
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| Part: | GTLP10B320 |
| Category: | Interface and Interconnect => Line Drivers/Interfaces |
| Description: | 10-Bit Lvttl/gtlp Transceiver With Split LVTTL Port And Feedback Path |
| Company: | Fairchild Semiconductor |
| Datasheet: | Download GTLP10B320 datasheet File size : 267 kB |
| Request For quote: | Find where to buy GTLP10B320
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Datasheet text preview:
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
May 2001 Revised May 2001
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output low level is typically less than 0.5V, the output level high is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on GTLP port (VERC) s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Split LVTTL inputs and outputs s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s A feedback path for control and diagnostics monitoring s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink -24mA/+24mA s B Port sink +50mA
Ordering Code:
Order Number GTLP10B320MTD Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500483
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GTLP10B320
Pin Descriptions
Pin Names OEB, OEC Description B Port, C Port Output Enable respectively (Active LOW)
Connection Diagram
VCC, GND, VREF Device Supplies LECLKAB, LECLKBC SEL SAB, SBC B0-B9 A0-A9 C0-C9 VERC A-to-B, B-to-C Latch CLK respectively (Transparent Active HIGH) Selects Internal Feedback Path Selects Register or Latch/Transparent Path for A-to-B and B-to-C respectively B Port GTLP I/O A Port LVTTL Inputs C Port LVTTL Outputs Edge Rate Control Pin (GND = Slow Edge Rate) (VCC = Fast Edge Rate)
Functional Description
The GTLP10B320 is a 10-bit Universal driver and receiver containing D-Type flip-flop, latch, and transparent modes of operation for the data paths. In addition there is an internal feedback path that can be used for diagnostic monitoring or caching schemes. Data flow in each direction is controlled by the clock signals (LECLKAB and LECLKBC) and output enables (OEB and OEC). The internal feedback path is controlled by the SEL pin and allows data transfer from Port A to Port C without requiring data to be output to the backplane. The internal feedback path is selected with SEL LOW and the B Port pin is selected with SEL HIGH. The data paths can also be configured for latch/transparent or register mode for each direction with the SAB and SBC pins. Data polarity is non-inverting with the GTLP outputs enabled via the OEB pin and the LVTTL outputs being enabled via the OEC pin. For A-to-B data flow the device is configured into a latch/ transparent or register mode by pin SAB. If SAB is LOW then the register mode is selected and the device operates on the LOW-to-HIGH transition of LECLKAB. If SAB is HIGH then the latch/transparent configuration is selected and a HIGH-to-LOW transition of LECLKAB stores data in the latch. If LECLKAB is HIGH the device is in transparent mode. When OEB is LOW the outputs are active and when OEB is HIGH the outputs are high impedance.
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GTLP10B320
Functional Tables
I/O Path: SEL = 1 (External Feedback Path) (Note 2) Inputs OEB 0 0 0 0 0 0 0 0 1 OEC 1 1 1 1 1 1 1 1 1 SAB 0 0 0 0 1 1 1 1 X S BC X X X X X X X X X LECLKAB LECLKBC Mode (AB) Register Register Register Register Latch Buffer Latch Buffer High Impedance An L H L H L L H H X Cn X X X X X X X X X Outputs Bn L H B0 (Note 1) B0 (Note 1) L L H H Z
L L
X X X X X X X X X
H
H X
Note 1: Output level before the indicated steady state input conditions were established. Note 2: The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used.
Internal Feedback Path: SEL = 0 (Internal Feedback Path) (Note 3) Inputs OEB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SAB 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 X S BC 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 X LECLKAB LECLKBC Mode (AB/BC) Register/Register Register/Register Register/Register Register/Register Register/Register Register/Register Register/Latch Register/Buffer Register/Latch Register/Buffer Register/Latch Register/Buffer Register/Latch Latch/Register Latch/Register Latch/Register Latch/Register Buffer/Register Buffer/Register Latch/Register Latch/Latch Latch/Latch Buffer/Buffer Buffer/Buffer High Impedance An L H X L H X L L H H X X X L H L H L H X L H L H X Bn L H L H L L H H Outputs Cn L H B0 (Note 4) B0 (Note 4) L L H H
L
L L L
B0 (Note 4) B0 (Note 4)
L
B0 (Note 4) B0 (Note 4)
L L L
H
H
H L
B0 (Note 4) B0 (Note 4) B0 (Note 4) B0 (Note 4) B0 (Note 4) B0 (Note 4) L H L H L H L H L H Z L H B0 (Note 4) B0 (Note 4) L H L H L H Z
H H L
L L
L
B0 (Note 4) B0 (Note 4)
H H X
H H X
Note 3: Function identical for SEL = 1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port. Note 4: Output level before the indicated steady state input conditions were established.
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