|
Details, datasheet, quote on part number:GTLP16612
| |
Datasheet text preview:
GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver
March 1995 Revised March 2001
GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic levels s Designed with an edge rate control circuit to reduce output noise on GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustability s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible Driver and Control inputs s Designed using Fairchild advanced CMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s 5V tolerant inputs and outputs on LVTTL port s Open drain on GTLP to support wired-or connection s Flow-through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port outputs source/sink
-32 mA/+32 mA
Ordering Code:
Order Number GTLP16612MEA GTLP16612MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS012390
www.fairchildsemi.com
GTLP16612
Pin Descriptions
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA CLKAB CLKBA VREF A1A18 Description A-to-B Output Enable (Active LOW) B-to-A Output Enable (Active LOW) A-to-B Clock Enable (Active LOW) B-to-A Clock Enable (Active LOW) A-to-B Latch Enable (Transparent HIGH) B-to-A Latch Enable (Transparent HIGH) A-to-B Clock Pulse B-to-A Clock Pulse GTLP Input Reference Voltage A-to-B TTL Data Inputs or B-to-A 3-STATE Outputs B1B18 B-to-A GTLP Data Inputs or A-to-B Open Drain Outputs
Connection Diagram
Functional Description
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A Port and control pins operate at LVTTL or 5V TTL levels while the B Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched and clock mode. The functional operation is described in the truth table below.
Truth Table
(Note 1) Inputs CEAB X L L X X L L H OE AB H L L L L L L L LEAB X L L H H L L L CL KAB X H L X X A X X X L H L H X Output B Z B0(Note 2) B0(Note 3) L H L H B0(Note 3) Clocked storage of A data Clock inhibit Latched storage of A data Transparent Mode
X
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established.
www.fairchildsemi.com
2
GTLP16612
Logic Diagram
3
www.fairchildsemi.com
|
|
