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Details, datasheet, quote on part number:GTLP16617MTDX
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Datasheet text preview:
GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
June 1997 Revised December 2000
GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
General Description
The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced CMOS technology s Bushold data inputs on the A port eliminates the need for external pull-up resistors on unused inputs. s Power up/down and power off high impedance for live insertion s 5 V tolerant inputs and outputs on the LVTTL port s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -32 mA/+32 mA s GTLP Buffered CLKAB signal available (CLKOUT)
Ordering Code:
Order Number GTLP16617MEA GTLP16617MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS500031
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GTLP16617
Pin Descriptions
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA VREF CLKAB CLKBA A1-A17 B1-B17 Description A-to-B Output Enable (Active LOW) B-to-A Output Enable (Active LOW) A-to-B Clock Enable (Active LOW) B-to-A Clock Enable (Active LOW) A-to-B Latch Enable (Transparent HIGH) B-to-A Latch Enable (Transparent HIGH) GTLP Reference Voltage A-to-B Clock B-to-A Clock A-to-B Data Inputs or B-to-A 3-STATE Data Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs CLKIN CLKOUT B-to-A Buffered Clock Output GTLP Buffered Clock Output of CLKAB
Connection Diagram
Functional Description
The GTLP16617 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 data bits. The output enables (OEAB and OEBA) control both the 17 bits of data and the CLKOUT/CLKIN buffered clock paths and the OEAB is synchronous with the CLKAB signal. The OEBA can not be synchronous since we are passing the clock through the device with data and we would need to generate the CLKBA signal elsewhere. It should also be noted that the OEAB register is controlled by CLKAB only, and is also not inhibited by the CEAB signal. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is registered LOW the outputs are active. When OEAB is registered HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used.
Truth Table
(Note 1) Inputs CEAB X L L X X L L H OEAB (Note 2) H L L L L L L L LEAB X L L H H L L L CLKAB A X X X L H L H X Output B Z (Note 3) B0 (Note 4) (Note 5) L H L H B0 (Note 5) Clocked storage of A data Clock inhibit Transparent Latched storage of A data Mode
H L X X
X
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, CEBA. Note 2: LH edge on CLKAB is required when changing the input on OEAB pin. Note 3: OEAB met set-up time prior to CLKAB LH transition Note 4: Output level before the indicated steady state input conditions were established, provided CLKAB was HIGH prior to LEAB going LOW. Note 5: Output level before the indicated steady state input conditions were established.
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GTLP16617
Logic Diagram
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