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Details, datasheet, quote on part number:GTLP16T1655
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Datasheet text preview:
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
August 1998 Revised December 2000
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on the GTLP backplane (VERC) s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -24mA/+24mA s B Port sink +100mA s Partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock s External pin to pre-condition I/O capacitance to high state (VCCBIAS)
Ordering Code:
Order Number GTLP16T1655MTD Package Number MTD64 Package Description 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS500172
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GTLP16T1655
Connection Diagram
Pin Descriptions
Pin Names 1OEAB 2OEAB 1OEBA 2OEBA OE 1LEAB 2LEAB 1LEBA 2LEBA VREF CLK 1A1-1A8 2A1-2A8 1B1-1B8 2B1-2B8 B Port I/O Byte 1 and Byte 2 Description A-to-B Output Enable (Active LOW) Byte 1 and Byte 2 B-to-A Output Enable (Active LOW) Byte 1 and Byte 2 Disables all I/O ports simultaneously A-to-B Latch Enable (Transparent HIGH) Byte 1 and Byte 2 B-to-A Latch Enable (Transparent HIGH) Byte 1 and Byte 2 GTLP Reference Voltage A-to-B and B-to-A Clock A Port I/O Byte 1 and Byte 2
Truth Tables
(Note 1) Inputs OE AB H L L L L L L L E AB X H H L L L L CL K X X X A X L H L H X X Output B Z L H L H B0 (Note 2) B0 (Note 3) High Impedance Transparent Transparent Registered Registered Previous State Previous State Mode
H L
Inputs OE L L L L H OE AB (Note 4) L L H H X OE BA (Note 4) L H L H X
Outputs A Port Active Z Active Z Z B Port Active Active Z Z Z
Inputs VERC VC C G ND
Output Edge B Port Slow Fast
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLK. Note 2: Output level before the indicated steady state input conditions were established, provided CLK was HIGH prior to LEAB going LOW. Note 3: Output level before the indicated steady state input conditions were established. Note 4: OEAB and OEBA are byte-wide enables. Each is proceeded by a number indicating the byte controlled.
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GTLP16T1655
Functional Description
The GTLP16T1655 is a high drive (100 mA) 16-bit universal bus transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. The device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output control signals but with a common clock pin (CLK) for both transceiver words. Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables (xOEAB and xOEBA) and clock (CLK). The output enables (1OEAB, 1OEBA, and 2OEAB and 2OEBA) control Byte1 and Byte2 data for the A to B and B to A directions respectively. For A-to-B data flow, the devices operate in the transparent mode when LEAB is HIGH. When LEAB transitions LOW, the A data is latched independent of CLK HIGH or LOW. If LEAB is LOW the A data is registered on the CLK LOW-to-HIGH transition. When OEAB is LOW the outputs are active. With OEAB HIGH the outputs are HIGH impedance. Data flow for the B-to-A direction is identical but uses OEBA, LEBA and CLK. Note that CLK is common to both directions and both 8-bit words. OE is also common and is used to disable all I/O ports simultaneously.
Logic Diagrams
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