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Details, datasheet, quote on part number:GTLP17T616
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Datasheet text preview:
GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
January 2000 Revised December 2000
GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -24mA/+24mA s B Port sink +50mA s GTLP buffered CLKAB signal available (CLKOUT)
Ordering Code:
Order Number GTLP17T616MEA GTLP17T616MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS500327
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GTLP17T616
Pin Descriptions
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA VR EF CLKAB CLKBA A1A17 B1B17 CL KIN CL KOUT Description A-to-B Output Enable (Active LOW) (LVTTL levels) B-to-A Output Enable (Active LOW) (LVTTL levels) A-to-B Clock/LE Enable (Active LOW) (LVTTL levels) B-to-A Clock/LE Enable (Active LOW) (LVTTL levels) A-to-B Latch Enable (Transparent HIGH) (LVTTL levels) B-to-A Latch Enable (Transparent HIGH) (LVTTL levels) GTLP Input Threshold Reference Voltage A-to-B Clock (LVTTL levels) B-to-A Clock (LVTTL levels) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs (GTLP Levels) B-to-A Buffered Clock Output (LVTTL levels) GTLP Buffered Clock Input/Output of CLKAB (GTLP Levels)
Connection Diagram
Truth Table (Note 1)
Inputs CEAB X L L X X L L OE AB H L L L L L L LEAB X L L H H L L CL KAB X H L X X A X X X L H L H Output B Z B0 (Note 2) B0 (Note 3) L H L H Clocked storage of A data H L L X X B0 (Note 3) Clock inhibit Latched storage of A data Transparent Mode
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established.
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GTLP17T616
Functional Description
The GTLP17T616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control the 17 bits of data and the CLKOUT/CLKIN buffered clock path. For A-to-B data flow, when CEAB is low, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are high impedance. The data flow of B-to-A is similar except that CEAB, OEBA, LEBA and CLKBA are used.
Logic Diagram
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