|Description||10A, 400V, 0.550 Ohm, N-channel Power MOSFET|
|Datasheet||Download IRF740 datasheet
|Cross ref.||Similar parts: STP11NK40Z, TK12A45D, CSD18502KCS, CSD18503KCS, CSD18504KCS, CSD18532KCS, CSD18533KCS, CSD18534KCS, CSD18537NKCS, CSD18542KCS|
This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. Formerly developmental type TA17424.Features
10A, 400V rDS(ON) = 0.550 Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"NOTE: When ordering, include the entire part number.
Absolute Maximum Ratings = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1). VDS Drain to Gate Voltage (RGS = 20k) (Note 1). VDGR Continuous Drain Current. 100oC. ID Pulsed Drain Current (Note 3). IDM Gate to Source Voltage. VGS Maximum Power Dissipation. PD Linear Derating Factor. Single Pulse Avalanche Energy Rating (Note 4). EAS Operating and Storage Temperature.TJ, TSTG Maximum Temperature for Soldering Leads 0.063in (1.6mm) from Case for 10s. TL Package Body for 10s, See Techbrief 334. Tpkg 300 260 UNITS W/oC mJ oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
= 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs tD(ON) tr tD(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Modified MOSFET Symbol Showing the Internal Devices Measured From the Drain Inductances D Lead, 6mm (0.25in) From Package to Center of Die LD Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad
TEST CONDITIONS VGS = 250µA (Figure 10) VGS = VDS, = 250µA VDS = Rated BVDSS, VGS = 0V VDS 0.8 x Rated BVDSS, VGS = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = ±20V VGS = 5.2A (Figures 8, 9) VDS = 5.2A (Figure 12) VDD = 20, VGS = 10V MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10A, VDS 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 1.0MHz (Figure 11)Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse-Transfer Capacitance Internal Drain InductanceThermal Resistance Junction to Case Thermal Resistance Junction to Ambient
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction DiodeSource to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES:
2. Pulse Test: Pulse width 300µs, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting = 25, peak IAS = 10A.FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
SINGLE PULSE t1 t2t2 NOTES: DUTY FACTOR: = t1/t2 PEAK TJ = PDM x ZJC TC t1, RECTANGULAR PULSE DURATION (S) 1 10 PDMFIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
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