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Details, datasheet, quote on part number:NC7SP57
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Datasheet text preview:
NC7SP57 · NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates
October 2001 Revised March 2003
NC7SP57 · NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates
General Description
The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild's Ultra Low Power (ULP) Series of TinyLogic. Ideal for applications where battery life is critical, this product is designed for ultra low power consumption within the VCC operating range of 0.9V to 3.6V. Each device is capable of being configured for 1 of 5 unique 2-input logic functions. Any possible 2-input combinatorial logic function can be implemented as shown in the Function Selection Table. Device functionality is selected by how the device is wired at the board level. Figure 1 through Figure 10 illustrate how to connect the NC7SP57 and NC7SP58 respectively for the desired logic function. All inputs have been implemented with hysteresis. The internal circuit is composed of a minimum of inverter stages including the output buffer, to enable ultra low dynamic power. The NC7SP57 and NC7SP58, for lower drive requirements, are uniquely designed for optimized power and speed, and are fabricated with an advanced CMOS technology to achieve best in class operation while maintaining extremely low CMOS power dissipation.
Features
s 0.9V to 3.6V VCC supply operation s 3.6V overvoltage tolerant I/O's at VCC from 0.9V to 3.6V s tPD 5 ns typ for 3.0V to 3.6V VCC 6 ns typ for 2.3V to 2.7V VCC 8 ns typ for 1.65V to 1.95V VCC 10 ns typ for 1.40V to 1.60V VCC 14 ns typ for 1.10V to 1.30V VCC 40 ns typ for 0.90V VCC s Power-Off high impedance inputs and outputs s Static Drive (IOH/IOL)
±2.6 mA @ 3.00V VCC ±2.1 mA @ 2.30V VCC ±1.5 mA @ 1.65V VCC ±1.0 mA @ 1.40V VCC ±0.5 mA @ 1.10V VCC ±20 µA @ 0.9V VCC
s Uses patented Quiet Series noise/EMI reduction circuitry s Ultra small MicroPak leadfree package s Ultra low dynamic power
Ordering Code:
Order Number NC7SP57P6X NC7SP57L6X NC7SP58P6X NC7SP58L6X Package Number MAA06A MAC06A MAA06A MAC06A Product Code Top Mark P57 K9 P58 L3 Package Description 6-Lead SC70, EIAJ SC88, 1.25mm Wide 6-Lead MicroPak, 1.0mm Wide 6-Lead SC70, EIAJ SC88, 1.25mm Wide 6-Lead MicroPak, 1.0mm Wide Supplied As 3k Units on Tape and Reel 5k Units on Tape and Reel 3k Units on Tape and Reel 5k Units on Tape and Reel
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation. Quiet Series and MicroPak are trademarks of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation
DS500701
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NC7SP57 · NC7SP58
Battery Life vs. VCC Supply Voltage
TinyLogic ULP and ULP-A with up to 50% less power consumption can extend your battery life significantly. Battery Life = (Vbattery *Ibattery*.9)/(Pdevice)/24hrs/day Where, Pdevice = (ICC * VCC) + (CPD + CL)* VCC2 * f Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at 10MHz, with CL = 15 pF load
Connection Diagrams
Pin Assignments for SC70
Pin Descriptions
Pin Name I0, I1, I2 Y Description Data Input Output
Function Table
Input I2 L L L (Top View) NC7SP57 and NC7SP58 Pin One Orientation Diagram L H H H H I1 L L H H L L H H I0 L H L H L H L H NC7SP57 NC7SP58 Y = (I0)·(I2)+(I1)·(I2) Y = (I0)·(I2)+(I1)·(I2) H L H L L L H H
L = LOW Logic Level
L H L H H H L L
H = HIGH Logic Level
AAA = Product Code Top Mark - see ordering code Note: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
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NC7SP57 · NC7SP58
Function Selection Table
2-Input Logic Function 2-Input AND 2-Input AND with inverted input 2-Input AND with both inputs inverted 2-Input NAND 2-Input NAND with inverted input 2-Input NAND with both inputs inverted 2-Input OR 2-Input OR with inverted input 2-Input OR with both inputs inverted 2-Input NOR 2-Input NOR with inverted input 2-Input NOR with both inputs inverted 2-Input XOR 2-Input XNOR Device Selection NC7SP57 NC7SP58 NC7SP57 NC7SP58 NC7SP57 NC7SP58 NC7SP58 NC7SP57 NC7SP58 NC7SP57 NC7SP58 NC7SP57 NC7SP58 NC7SP57 Connection Configuration Figure 1 Figures 7, 8 Figure 4 Figure 6 Figures 2, 3 Figure 9 Figure 9 Figures 2, 3 Figure 6 Figure 4 Figures 7, 8 Figure 1 Figure 10 Figure 5
Logic Configurations NC7SP57
Figure 1 through Figure 5 show the logical functions that can be implemented using the NC7SP57. The diagrams show the DeMorgan's equivalent logic duals for a given 2-input function. Next to the logical implementation is the board level physical implementation of how the pins of the function should be connected.
FIGURE 1. 2-Input AND Gate
FIGURE 2. 2-Input NAND with Inverted A Input
FIGURE 3. 2-Input NAND with Inverted B Input
FIGURE 4. 2-Input NOR Gate
FIGURE 5. 2-Input XNOR Gate
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