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Details, datasheet, quote on part number:NM25C160LVM8
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Datasheet text preview:
NM25C160 16K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
March 1999
NM25C160 16K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C160 is a 16,384-bit CMOS EEPROM with an SPI compatible serial interface. The NM25C160 is designed for data storage in applications requiring both non-volatile memory and insystem data updates. This EEPROM is well suited for applications using the 68HC11 series of microcontrollers that support the SPI interface for high speed communication with peripheral devices via a serial bus to reduce pin count. The NM25C160 is implemented in Fairchild Semiconductor's floating gate CMOS process that provides superior endurance and data retention. The serial data transmission of this device requires four signal lines to control the device operation: Chip Select (CS), Clock (SCK), Data In (SI), and Serial Data Out (SO). All programming cycles are completely self-timed and do not require an erase before WRITE. BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection. Additionally, separate WRITE enable and WRITE disable instructions are provided for data protection. Hardware data protection is provided by the WP pin to protect against inadvertent programming. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence.
Features
s 2.1 MHz clock rate @ 2.7V to 5.5V s 16,384 bits organized as 2,048 x 8 s Multiple chips on the same 3-wire bus with separate chip select lines s Self-timed programming cycle s Simultaneous programming of 1 to 16 bytes at a time s Status register can be polled during programming to monitor READY/BUSY s Write Protect (WP) pin and write disable instruction for both hardware and software write protection s Block write protect feature to protect against accidental writes s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Block Diagram
CS HOLD SCK SI Instruction Register Instruction Decoder Control Logic and Clock Generators VCC VSS WP
Address Counter/ Register
Program Enable VPP EEPROM Array 16,384 Bits (2048 x 8)
High Voltage Generator and Program Timer
Decoder 1 of 2048
Read/Write Amps
Data In/Out Register 8 Bits
Data Out Buffer
SO
Non-Volatile Status Register
DS012402-1
© 1999 Fairchild Semiconductor Corporation NM25C160 Rev. D.1
1
www.fairchildsemi.com
NM25C160 16K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8) CS SO WP VSS 1 2 NM25C160 3 4 6 5 SCK SI
DS012402-2
8 7
VCC HOLD
Top View See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
CS SO WP VSS SI SCK HOLD VCC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply
Ordering Information NM 25 C XX LZ E XX
Package
Letter
N M8 MT8 None V E Blank L LZ 160 C Interface 25 NM
Description
8-pin DIP 8-pin SO 8-pin TSSOP 0 to 70°C -40 to +125°C -40 to +85°C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V and <1µA Standby Current 16K, mode 0 CMOS technology SPI Fairchild Nonvolatile Memory Prefix
Temp. Range
Voltage Operating Range
Density/Mode
2
NM25C160 Rev. D.1
www.fairchildsemi.com
NM25C160 16K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Standard Voltage 4.5 VCC 5.5V Specifications Operating Conditions Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating -65°C to +150°C +6.5V to -0.3V +300°C 2000V Ambient Operating Temperature NM25C160 NM25C160E NM25C160V Power Supply (VCC) 0°C to +70°C -40°C to +85°C -40°C to +125°C 4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V VCC 5.5V (unless otherwise specified)
Symbol
ICC ICCSB IIL IOL VIL V IH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage CMOS Input Low Voltage CMOS Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min CS High Time CS Setup Time Data Setup Time HOLD Setup Time CS Hold Time Data Hold Time HOLD Hold Time Output Delay Output Hold Time HOLD to Output Low Z Output Disable Time HOLD to Output High Z Write Cycle Time
Conditions
CS = VIL CS = VCC VIN = 0 to VCC VOUT = GND to VCC
Min
Max
3 50
Units
mA µA µA µA V V V V
-1 -1 -0.3 0.7 * VCC
+1 +1 VCC * 0.3 VCC + 0.3 0.4
IOL = 1.6 mA IOH = -0.8 mA VCC - 0.8
2.1 2.0 2.0 (Note 2) (Note 2) (Note 3) 190 190 240 240 100 90 240 100 90 CL = 200 pF 0 100 CL = 200 pF 240 100 116 Bytes 10 240
MHz µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200 pF 0.1 * VCC 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ Max Units
3 2 8 6 pF pF
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns. Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 4: This parameter is periodically sampled and not 100% tested.
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NM25C160 Rev. D.1
www.fairchildsemi.com
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