Details, datasheet, quote on part number: RC4200AN
DescriptionAnalog Multiplier
CompanyFairchild Semiconductor
DatasheetDownload RC4200AN datasheet
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Features, Applications


High accuracy Nonlinearity 0.1% Temperature coefficient 0.005%/C Multiple functions Multiply, divide, square, square root, RMS-to-DC conversion, AGC and modulate/demodulate Wide bandwidth 4 MHz Signal-to-noise ratio 94 dB


The RC4200 analog multiplier has complete compensation for nonlinearity, the primary source of error and distortion. This multiplier also has three onboard operational amplifiers designed specifically for use in multiplier logging circuits. These amplifiers are frequency compensated for optimum AC response in a logging circuit, the heart of a multiplier, and can therefore provide superior AC response. The RC4200 can be used in a wide variety of applications without sacrificing accuracy. Four-quadrant multiplication, two-quadrant division, square rooting, squaring and RMS conversion can all be easily implemented with predictable accuracy. The nonlinearity compensation is not just trimmed at a single temperature, it is designed to provide compensation over the full temperature range. This nonlinearity compensation combined with the low gain and offset drift inherent in a well-designed monolithic chip provides a very high accuracy and a low temperature coefficient.


Low distortion audio modulation circuits Voltage-controlled active filters Precision oscillators

The RC4200 multiplier is designed to multiply two input currents (I1 and I2) and to divide by a third input current (I4). The output is also in the form of a current (I3). A simplified circuit diagram is shown in the Block Diagram. The nominal relationship between the three inputs and the output is: -------I4 (1)

Previous multiplier designs have suffered from an additional undesired linear term in the above equation; the collector current times the emitter resistance. The ICrE term introduces a parabolic nonlinearity even with matched transistors. Fairchild Semiconductor has developed a unique and proprietary means of inherently compensating for this undesired ICrE term. Furthermore, this Fairchild Semiconductor developed circuit technique compensates linearity error over temperature changes. The nonlinearity versus temperature is significantly improved over earlier designs. From equation (2) and by assuming equal transistor junction temperatures, summing base-to-emitter voltage drops around the transistor array yields: In -----I S4 q This equation reduces to: I2 = -------------I I3 I4

The three input currents must be positive and restricted to a range to 1 mA. These currents go into the multiplier chip at op amp summing junctions which are nominally at zero volts. Therefore, an input voltage can be easily converted to an input current by a series resistor. Any number of currents may be summed at the inputs. Depending on the application, the output current can be converted to a voltage by an external op amp or used directly. This capabilty of combining input currents and voltages in various combinations provides great versatility in application. Inside the multiplier chip, the three op amps make the collector currents of transistors Q1, Q2 and Q4 equal to their respective input currents (I1, I2, and I4). These op amps are designed with current source outputs and are phase-compensated for optimum frequency response as a multiplier. Power drain of the op amps was minimized to prevent the introduction of undesired thermal gradients on the chip. The three op amps operate on a single supply voltage (nominally -15V) and total quiescent current drain is less than 4 mA. These special op amps provide significantly improved performance in comparison 741-type op amps. The actual multiplication is done within the log-antilog configuration of the Q1-Q4 transistor array. These four transistors, with associated proprietary circuitry, were specially designed to precisely implement the relationship. - In -------V BEN = -----Q SN (2)

The rate of reverse saturation current IS1IS2/IS3IS4, depends on the transistor matching. In a monolithic multiplier this matching is easily achieved and the rate is very close to unity, typically 1.01%. The final result is the desired relationship: -------I4 (5)

The inherent linearity and gain stability combined with low cost and versatility makes this new circuit ideal for a wide range of nonlinear functions.

Parameter Supply Voltage Input Current Storage Temperature Range Operating Temperature Range -55 0

Notes: 1. For a supply voltage greater than -22V, the absolute maximum input voltage is equal to the supply voltage. 2. Observe package thermal characteristics.

(Still air, soldered into PC board) 8-Lead Plastic DIP Maximum Junction Temperature Maximum < 50C Thermal Resistance JC Thermal Resistance JA For > 50C Derate 6.25mW/C 8-Lead SOIC 240C/W 4.17mW/C

(Over operating temperature range, = -15V unless otherwise noted) 4200A Parameters Total Error as Multiplier Test Conditlons +25C Untrimmed1 With External Trim Versus Temperature Versus Supply -18V) Nonlinearity2 Input Current Range (I1, I2 and I4) Input Offset Voltage Input Bias Current Average Input Offset Voltage Drift Output Current Range I1,2,4 250 A, = +25C %/C %/V mV nA Min. Typ. Max. Min. 4200 Typ. Max. Units


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