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Details, datasheet, quote on part number:RMPA2450
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Datasheet text preview:
RMPA2450
May 2004
RMPA2450
2.42.5 GHz GaAs MMIC Power Amplifier
General Description
The Fairchild RMPA2450 is a fully monolithic power amplifier in a surface mount package for use in wireless applications in the 2.4 to 2.5GHz ISM frequency band. The amplifier may be biased for linear, class AB or class F for high efficiency applications. On-chip matching components allow operation in a 50 system with no external matching components. The MMIC chip design utilizes our 0.25µm power PHEMT process.
Features
· · · · · · 35% Power Added Efficiency 31dBm Output Power (P1dB) at Vd = +7V 28dBm Output Power (P1dB) at Vd = +5V No external RF matching components Small Package Outline: 0.28" x 0.28" x 0.07" Thermal Resistance (Channel to Case): 33°C/W
Device
Absolute Ratings
Symbol Vd1, Vd2 Vg1, Vg2 VdVg PIN Ids Ig Tch TCASE TSTG Parameter Positive Drain DC Voltage Negative Gate DC Voltage Simultaneous Drain to Gate Voltage RF Input Power (from 50 source) Drain to Source Current Gate Current Channel Temperature Operating Case Temperature Storage Temperature Range Rating +8 -5 +10 +10 575 5 150 -40 to 100 -40 to 125 Units V V V dBm mA mA °C °C °C
©2004 Fairchild Semiconductor Corporation
RMPA2450 Rev. C
RMPA2450
Electrical Characteristics (Note 4, At 25°C, ZO = 50, Unless Otherwise Noted)
Parameter Frequency Range Gain1, 2, 4 Output Power, P1dB1,4 Assoc. Power Added Efficiency Output Power, P1dB3 Assoc. Power Added Efficiency Drain Current (Idd1 + Idd2) Gate Current (Igg1 + Igg2) Input Return Loss (50) Min 2400 Typ 2450 30 28 35 31 33 Max 2500 Units MHz dB dBm % dBm % mA mA dB
550 5 7.5
Notes: 1: Idq = 360mA, Vd1 = Vd2 = 5.0V 2: Pin = -3dBm, 3: Vd1 = Vd2 = +7V 4: Production Testing includes Gain, Output Power (P1dB) and Input Return Loss at Vd1 = Vd2 = 5.0V, Vg1 = Vg2 = -0.5V (nominal) , adjusted for Idq = 360mA, Pin = -3 dBm and at F = 2.45 GHz. Other Parameters are guaranteed by Design Validation Testing.
Vd1 Pin# 5
Vd2 Pin# 4
Ground Pin# 1, 3, 6, 7, 9, 12, 13
RF IN Pin# 8
RF OUT Pins# 2
Vg1 Pin# 10
Vg2 Pin# 11
Figure 1. Functional Block Diagram (RMPA2450) TOP VIEW 0.200 SQ. BOTTOM VIEW 654 A 8 0.030 9 10 11 PLASTIC LID 0.010 0.230 0.246 0.282 SIDE SECTION Figure 2. Outline Dimensions (RMPA2450)
©2004 Fairchild Semiconductor Corporation RMPA2450 Rev. C
45 6 3 3 2 1 12 11 10 0.069 MAX. 7 8 9 0.041
7
RMPA 2450
2 1 12
0.015
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13
Description GND RF Out GND Vd2 Vd1 GND GND RF GND Vg1 Vg2 GND GND (PACKAGE BASE)
Dimensions in inches
RMPA2450
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE. The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount package. It may be noted that the chip is a fully monolithic amplifier for ISM band applications. Figure 1 shows the functional block diagram of the packaged product.
Test Procedure for the Evaluation Board (RMPA2450-TB)
The following sequence of procedure must be followed to properly test the power amplifier: CAUTION: LOSS OF GATE VOLTAGES (VG1, VG2) WHILE DRAIN VOLTAGES (VD1,VD2) ARE PRESENT MAY DAMAGE THE AMPLIFIER. Step 1: Turn off RF input power. Step 2: Use GND terminal of the evaluation board for DC supplies. Apply gate supply voltages of typical -0.5V to evaluation board terminals Vgg. Step 3: Apply drain supply voltages of +5.0V to evaluation board terminals Vdd. Adjust gate supply voltage, if needed, to set the desired quiescent bias currents Idq (or to the values as shown on the data summary accompanying the product samples). Step 4: After the bias condition is established, RF input signal may now be applied. Step 5: Follow turn-off sequence of: (i) Turn off RF Input Power (ii) Turn down and off Vdd (iii) Turn down and off Vgg
Test Fixture
Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing external bias components is shown in Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the schematic diagram. The following should be noted: (1) Package pin designations are as shown in Figure 2. (2) Vg1, Vg2 are the Gate Voltages (negative) applied at the pins of the package (3) Vgg1 = Vgg2 = Vgg is the negative supply voltage at the evaluation board terminal (4) Vd1, Vd2 are the Drain Voltages (positive) applied at the pins of the package (5) Vdd1 = Vdd2 = Vdd is the positive supply voltage at the evaluation board terminal
©2004 Fairchild Semiconductor Corporation
RMPA2450 Rev. C
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