Details, datasheet, quote on part number: SSTVN16857
Description14-Bit Register With SSTL-2 Compatible I/o (Preliminary)
CompanyFairchild Semiconductor
DatasheetDownload SSTVN16857 datasheet


Features, Applications

The a 14-bit register designed for use with 184 and 232 pin PC1600, 2100, and 2700 DDR DIMM applications. The a 14-bit register designed for use with 184 and 232 pin PC3200 DDR DIMM applications. These devices have a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. These devices have been designed for compliance with the JEDEC DDR module and register specifications. The devices are fabricated on an advanced submicron CMOS process and are designed to operate at power supplies of less than 3.6V's.


s Compliant with DDR-I registered module specifications s Operates 0.2V VDD s SSTL-2 compatible input and output structure s Differential SSTL-2 compatible clock inputs s Low power mode when device is reset s Industry standard 48 pin TSSOP package

Order Number SSTV16857MTD SSTVN16857MTD (Preliminary) Package Number MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Pin Name Q1-Q14 D1-D14 RESET CK VREF VDDQ VDD Description SSTL-2 Compatible Output SSTL-2 Compatible Inputs Asynchronous LVCMOS Reset Input Positive Master Clock Input Negative Master Clock Input Voltage Reference Pin for SSTL Level Inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs

L = Logic LOW H = Logic HIGH X = Don't Care, but not floating unless noted = LOW-to-HIGH Clock Transition = HIGH-to-LOW Clock Transition

The SSTV16857 and SSTVN16587 are 14-bit registers with SSTL-2 compatible inputs and outputs. Input data is captured by the register on the positive edge crossing of the differential clock pair. When the LV-CMOS RESET signal is asserted LOW, all outputs and internal registers are asynchronously placed into the LOW logic state. In addition, the clock and data differential comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16857/ SSTVN16857 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal.

Supply Voltage (VDDQ) Supply Voltage (VDD) Reference Voltage (VREF) Input Voltage (VI) Output Voltage (VO) Outputs Active (Note 2) DC Input Diode Current (IIK) VI > VDD DC Output Diode Current (IOK) VO > VDD DC Output Source/Sink Current (IOH/IOL) DC VDD or Ground Current per Supply Pin (IDD or Ground) Storage Temperature Range (Tstg)

Power Supply (VDDQ) SSTV16857 SSTVN16857 Power Supply (VDD) Operating Range Reference Supply (VREF SSTV16857 SSTVN16857 Termination Voltage (VTT) Input Voltage Output Voltage (VO) Output in Active States Output Current IOH/IOL VDD to 2.7V VDD 0V to VDDQ to 1.35 VREF 0V to VDD VDDQ to 2.7V

Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW.

Symbol VIKL VIKH VIH-AC VIL-AC VIH-DC VIL-DC VIH VIL VICR VI(PP) VOH VOL II IDD Parameter Input LOW Clamp Voltage Input HIGH Clamp Voltage AC HIGH Level Input Voltage AC LOW Level Input Voltage DC HIGH Level Input Voltage DC LOW Level Input Voltage HIGH Level Input Voltage LOW Level Input Voltage Common Mode Input Voltage Range Peak to Peak Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Static Standby Static Operating Conditions +18 mA Data Inputs Data Inputs Data Inputs Data Inputs RESET CLK, CLK CLK, CLK IOH -100 A IOH -16 mA IOL 100 A IOL VI = VDD or GND RESET = GND, = 0 RESET = VDD, VI = VIH(AC) or VIL(AC) 2.3 to VDD VREF+150mV VREF-150mV VDD (V) VREF+310mV VREF-310mV Min Max -1.2 3.5 Units V A


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