|
Details, datasheet, quote on part number:X5001
| |
| Part: | X5001 |
| Category: | Power Management => Supervisory Circuits => Microprocessor Supervisors => Watchdog |
| Description: | Cpu Supervisor With Selectable Watchdog Timer Adjustable Low Voltage Reset, Active Low, Spi Interface |
| Company: | Fairchild Semiconductor |
| Datasheet: | Download X5001 datasheet File size : 122 kB |
| Request For quote: | Find where to buy X5001
|
| |
Datasheet text preview:
64K
X46402
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
DESCRIPTION
The X46402 combines several functions into one device. The first is a dual voltage CPU supervisor plus 64Kbit serial EEPROM memory with password protected write and read operations. The size of the password protected area is selectable by 3 control bits. A Write Protect (WP) pin in conjunction with a WPEN bit provides hardware OTP control of the configuration of the array. Password protected areas require 64 bit read or write passwords prior to access. A secondary voltage monitor circuit activates a V2FAIL pin when the secondary supply voltage drops below a V2trip voltage. This circuit is primarily intended to detect the immediate loss of the battery supply. A low VCC voltage detect circuit activates a RESET pin when VCC drops below a VTRIP voltage. This signal also blocks read or write operations. A watchdog timer with the time period controlled by three bits provides several possible time out periods from 150ms to 1 minute.
FEATURES · Dual Voltage Detection and Reset Assertion -- Low VCC monitor -- Low V2MON monitor -- Low VCC block of EEPROM writes -- RESET signal valid down to VCC=1V · Selectable Watchdog Timer -- 150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF · Volatile Flag Shows Watchdog/Low Voltage Reset · 64kbit 2-Wire Serial EEPROM -- 1MHz serial interface speed -- 64-byte page write mode · Two 64-Byte OTP Memory Blocks -- Requires 64-bit OTP password to write · Adjustable Size Password Protected Array -- 64 bit read and write array passwords --Non-password protected array area · 8 Count Tamper Counter for Invalid Passwords · Operates at 2.5-3.7V · 8L TSSOP package
BLOCK DIAGRAM
WP Write Control Password Logic HV Generation Timing and Control Write Password Area (Bytes) (64, 128, 256, 512, 2K, 4K, All, None) No Password Area Control OTP array 1 OTP array 2 Passwords Y Decoder Data Register (VCC) Control Signal EEPROM Array (64Kbits) Watchdog Timer Reset Reset & Watchdog Timebase Power on and Low Voltage Reset Generation V2FAIL
+ -
RESET
SCL SDA
Command Decode and Control Logic
X Decoder
V2MON V2TRIP VCC VTRIP
+ -
Xicor, Inc. 2000 Patents Pending 9900-3003.5 5/30/00 EP
Characteristics subject to change without notice.
1 of 23
X46402
PACKAGE/PINOUTS
8L TSSOP VSS WP SDA RESET 1 2 3 4 8 7 6 5 VCC V2MON SCL V2FAIL
V2 Voltage Fail Output (V2FAIL) V2FAIL is an active LOW, open drain output which goes active whenever V2MON falls below the minimum V2trip sense level. It will remain active until V2MON rises above the minimum V2MON sense level. DEVICE OPERATION Power On Reset Application of power to the X46402 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X46402 monitors the VCC and V2MON levels and compares these with internal, preset voltages. When the internal low voltage detect circuitry senses that V2MON is low, the V2FAIL pin goes active. Typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in preparation for an impending power failure. When the internal low voltage detect circuitry senses that VCC is low, the following happens: The RESET pin goes active. The Flag bit in the control register is set to zero. Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to complete the operation. The RESET and V2FAIL signals remain active until VCC voltage drops below 1V. RESET remains active until VCC returns and exceeds VTRIP for 200ms. V2FAIL remains active until immediately after V2MON returns and exceeds it's minimum voltage.
PIN NAMES
VSS SDA VCC SCL WP V2MON RESET V2FAIL Ground Serial Data Power Serial Clock Write Protect Voltage monitor input Low Voltage Detect Output V2 Voltage Fail Output
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with other open drain or open collector outputs. An open drain requires the use of a pull-up resistor. Write Protect (WP) The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the Watchdog Timer control and the memory write protect bits. Reset Output (RESET) RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vtrip sense level. It will remain active until Vcc rises above the minimum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the selectable Watchdog time-out period. A serial start bit will reset the Watchdog Timer. RESET also goes active on power up at 1V and remains active for 150ms after the power supply stabilizes.
Characteristics subject to change without notice.
2 of 23
X46402
µC Volt Reg OTP Mode Enabled Pin1 VCC VSS V2MON WP SCL SDA RESET V2FAIL VCC
Control Register A password protected read or write array command at address FFFFh reads or writes the Control Register. Since the control register contains information relating to the password protection, it is necessary to use the Array passwords to access the control register. The Control Register contains bits that control the watchdog timer and the hardware write protect features and is formatted as follows: 7
WPEN
SCL SDA INTR RESET
6
FLB
5
4
3
2
BL2
1
BL1
0
BL0
Recommended Connection
WD2 WD1 WD0
Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the Start bit. The microprocessor must send a start bit periodically to prevent a RESET signal. The start bit must occur prior to the expiration of the watchdog time-out period. The state of three nonvolatile control bits in the Control Register determines the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin HIGH and setting the WPEN bit HIGH. ARCHITECTURE Data Memory This 64kbit memory array can be partitioned into password protected or non-password protected areas. When password protected, the contents are readable after sending a "Memory Read" password. The contents of a password protected portion of the memory array are writeable with a "Memory Write" Password. This array is re-writable up to the limit of the EEPROM endurance. OTP The second section of memory consists of two 64-byte arrays, each writable only once. These arrays are always password protected. Reading from either of these arrays requires the use of an "OTP Read" password. Both arrays can be read with a single operation. Writing either array requires an "OTP Write" Password. Writing more than 64 bytes to each array results in the data "wrapping" around and over-writing previous values. Array
OTP Array 1 OTP Array 2
Write Protect Enable bit (WPEN) The WP pin, in conjuction with a WPEN bit programmed HIGH, provides Hardware Write Protection. This prevents changes to the control register contents even with a valid password. When either the WP pin or WPEN bit is LOW, a 64 bit Array write array password is required to change the contents of the control register. When both the WP pin and the WPEN bit are HIGH, the Control Register cannot be written. Flag Bit The flag bit is a volatile bit. It can be used to determine if a reset condition was due to a power failure or watchdog reset condition. If power fails (i.e. the internal low voltage detect signal goes active), the bit is set to '0'. This bit is also set or reset by a Control Register write operation. A watchdog reset does not change the state of the flag bit. Watchdog Timer Control The Watchdog time-out period is controlled by the bits WD2, WD1, and WD0. See the following Table. Table 1. Watchdog Time Control Bits Control Register Bits WD2 WD1 WD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Watchdog Time-Out (Typical) 1 Second 450 Milliseconds 150 Milliseconds Disabled 1 minute 20 seconds 10 seconds 5 seconds
Address
0000h - 003Fh 0040h - 007Fh
Characteristics subject to change without notice.
3 of 23
|
|
