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Details, datasheet, quote on part number:FT8U245AM
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Datasheet text preview:
FT8U245AM
USB FIFO - Fast Parallel Data Transfer IC FEATURES
· · · · · Single Chip Fast Data Transfer Solution Send / Receive Data over USB at up to 1 M Bytes / sec 384 byte FIFO Transmit buffer / 128 byte FIFO receive buffer for high data throughput Simple interface to CPU or MCU bus No in-depth knowledge of USB required as all USB Protocol is handled automatically within the I.C. · FTDI's Virtual COM port drivers eliminate the need for USB driver development in most cases. · · · · Compact 32 pin ( 7mm x 7mm ) MQFP package Integrated 6MHz - 48MHz Clock Multiplier aids FCC and CE compliance Integrated 3.3v Regulator No External Regulator Required 4.4v .. 5.25v Single Supply Operation · · · · UHCI / OHCI Compliant USB 1.1 Specification Compliant USB VID, PID, Serial Number and Product Description Strings in external E2PROM. Virtual COM Port Drivers for Windows 98 and Windows 98 SE Windows 2000 Windows Millennium ** Apple iMAC ** Linux ** Application Areas USB ISDN and ADSL Modems High Speed USB
Ù PDA Communications
USB I/F for Digital Cameras USB I/F for MP3 players
Ù USB data transfer cables USB Ù USB null-modem cables
USB
High Speed USB Instrumentation
GENERAL DESCRIPTION
The FT8U245AM provides an easy cost-effective method of transferring data to / from a peripheral and a host P.C. at up to 8 Million bits ( 1 Megabyte ) per second. It's simple FIFO-like design makes it easy to interface to any CPU ( MCU ) either by mapping the device into the Memory / IO map of the CPU, using DMA or controlling the device via IO ports. To send data from the peripheral to the host P.C. simply write the byte wide data into the device when the transmitter empty status bit is not active. If the ( 384 byte ) transmit buffer fills up, the device de-asserts transmit empty in order to stop further data being written to the device until some of the FIFO data has been transferred over USB. When the host P.C. sends data to the peripheral over USB, the device will assert the receiver full status bit to let the peripheral know that data is available. The peripheral then reads the data until the receiver full status bit goes inactive, indicating no more data is available to read. By using FTDI's virtual COM Port drivers, the peripheral looks like a standard COM Port to the application software. Commands to set the baud rate are ignored the device always transfers data at it's fastest rate regardless of the application's baud rate setting.
Future Technology Devices Intl.
FT8U245AM Preliminary Information Rev 0.9 Subject to Change
Figure 1 FT8U245AM Block Diagram ( Simplified )
VCC
3V3OUT
3.3 Volt LDO Regulator
FIFO Receive Buffer 128 Bytes
USBDP USB Transceiver USBDM Serial Interface Engine ( SIE ) USB Protocol Engine FIFO Controller
D0 D1 D2 D3 D4 D5 D6 D7 RD# WR RXF# TXE#
USB DPLL
FIFO Transmit Buffer 384 Bytes
EEREQ# EEGNT#
XTOUT 6MHZ Oscillator XTIN x8 Clock Multiplier
48MHz
GND RESET#
EEPROM Interface
EECS EESK EEDATA
12MHz
TEST
RCCLK
Figure 2 FT8U245AM I.C. Pinout
RCCLK
EECS
AVCC
AGND
XTOUT
XTIN
VCC
32 EESK EEDATA VCC RESET# TEST 3V3OUT USBDP USBDM 8 9 1
25 24 D1 D2 D3 D4 D5 D6 D7 17 16 GND
FTDI
FT245AM
XXYY
EEREQ#
EEGNT#
VCC
GND
RXF#
TXE#
Future Technology Devices Intl.
FT8U245AM Preliminary Information Rev 0.9 Subject to Change
RD#
WR
D0
FT8U245AM - FUNCTIONAL BLOCK DESCRIPTION
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3.3V LDO Regulator The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin.
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USB Transceiver The USB Transceiver Cell provides the USB 1.1 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection.
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USB DPLL The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block.
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6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the X8 Clock multiplier from an external 6MHz crystal or ceramic resonator.
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X8 Clock Multiplier The X8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 48MHz reference clock for the USB DPPL and the Baud Rate Generator blocks.
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Serial Interface Engine ( SIE ) The Serial Interface Engine ( SIE ) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 1.1 specification, it performs bit stuffing / un-stuffing and CRC5 / CRC16 generation / checking on the USB data stream.
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USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol ( Chapter 9 ) requests generated by the USB host controller and the commands for controlling the functional parameters of the UART.
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Fifo Receive Buffer ( 128 bytes ) Data sent from the USB Host to the FIFO via the USB data out endpoint is stored in the FIFO Receive Buffer and is removed from the buffer by reading the FIFO contents using RD#.
Future Technology Devices Intl.
FT8U245AM Preliminary Information Rev 0.9 Subject to Change
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