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Part: MB84VA2000-10
Category:
Memory
-> Flash
Description: 8m ( X 8 ) Flash Memory & 2m ( X 8 ) Static RAM
Company: Fujitsu Microelectronics, Inc.
Datasheet: Download MB84VA2000-10 datasheet File size : 413 kB
Request For quote: Find where to buy MB84VA2000-10
Datasheet text preview:
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50101-2E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (× 8) FLASH MEMORY & 2M (× 8) STATIC RAM
MB84VA2000-10/MB84VA2001-10
s FEATURES
· Power supply voltage of 2.7 to 3.6 V · High performance 100 ns maximum access time · Operating Temperature 20 to +85°C -- FLASH MEMORY · Minimum 100,000 write/erase cycles · Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. · Boot Code Sector Architecture MB84VA2000: Top sector MB84VA2001: Bottom sector · Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector · Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address · Data Polling and Toggle Bit feature for detection of program or erase cycle completion · Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion · Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. · Low VCC write inhibit 2.5 V · Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device · Please refer to "MBM29LV800TA/BA" data sheet in detailed function -- SRAM · Power dissipation Operating : 35 mA max. Standby : 50 µA max. · Power down features using CE1s and CE2s · Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VA2000-10/MB84VA2001-10
s BLOCK DIAGRAM
VCCf A0 to A19 A0 to A19 RESET CEf
VSS
RY/BY 8 M bit Flash Memory
DQ0 to DQ7 VCCs A0 to A17 VSS
WE OE CE1s CE2s
2 M bit Static RAM
2
MB84VA2000-10/MB84VA2001-10
s PIN ASSIGNMENTS
(Top View) A
6 5 4 3 2 1 CE1s A10 OE A11 A14 WE
B
VSS DQ5 DQ7 A8 A18 VCCs
C
DQ1 DQ2 DQ4 A5 N.C. A17
D
A1 A0 DQ0 N.C. CEf VSS
E
A2 A3 A6 DQ3 N.C. N.C.
F
A4 A7 A19 N.C. VCCf N.C.
G
CE2s RY/BY RESET A13 DQ6 N.C.
H
A9 A15 A16 N.C. A12 N.C.
Table 1 Pin Configuration
Pin A0 to A17 A18 to A19 DQ0 to DQ7 CEf CE1s CE2s OE WE RY/BY RESET N.C. VSS VCCf VCCs
F unction Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Hardware Reset Pin/Sector Protection Unlock (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM)
Input/ Output I I I/O I I I I I O I -- Power Power Power
3
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