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Part: GLT440L04-50J3
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
Description:
Company: G-Link Technology Corporation
Datasheet: Download GLT440L04-50J3 datasheet File size : 150 kB
Request For quote: Find where to buy GLT440L04-50J3
Datasheet text preview:
G -LINK
GLT440L04
1M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec. 2001 (Rev. 1.1)
Features : 1,048,576 words by 4 bits organization.
Fast access time and cycle time Low power dissipation. Read-Modify-Write, RAS -Only Refresh,
CAS -Before- RAS Refresh, Hidden Refresh.
Description :
The GLT440L04 is a high-performance CMOS dynamic random access memory containing 4,194,304 bits organized in a x4 configuration. The GLT440L04 offers page cycle access with Extended Data Output. The GLT440L04 has 10 row- and 10 columnaddresses, and accepts 1024-cycle refresh in 16 ms. The GLT440L04 provides EDO PAGE MODE operation which allows for fast data access within a row-address defined boundary, up to 1024 x 4 bits with cycle times as short as 20ns.
1,024 refresh cycles per 16ms. Available in 300 mil 20/26pin SOJ and
TSOPII.
3.3V±0.3V Vcc Power Supply voltage. All inputs and Outputs are LVTTL
compatible. Extended Data-Out (EDO) Page access cycle.
Self-refresh Capability. Extended Temperature Available (-25°C~85°C)
HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time (tCAC)
50 50 ns 25 ns 20 ns 84 ns 13 ns
60 60 ns 30 ns 25 ns 104 ns 15 ns
70 70 ns 35 ns 30 ns 124 ns 20 ns
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F,No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Tawian.
-1-
G -LINK
GLT440L04
1M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec. 2001 (Rev. 1.1)
Pin Configuration :
GLT440L04 300mil 26(20) TSOPII
VSS DQ3 DQ2 CAS OE
GLT440L04 300mil 26(20) SOJ
DQ0 DQ1 WE RAS A9 1 2 3 4 5 20 19 18 17 16
DQ0 DQ1 WE RAS A9
1 2 3 4 5
20 19 18 17 16
VSS DQ3 DQ2 CAS OE
A0 A1 A2 A3 VCC
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
A0 A1 A2 A3 V CC
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
Pin Descriptions: Name A0 - A9
RAS CAS WE OE
Function Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Inputs / Outputs +3.3V Power Supply Ground No Connection
DQ0 - DQ3 VCC VSS NC
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F,No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Tawian.
-2-
G -LINK
GLT440L04
1M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec. 2001 (Rev. 1.1)
Absolute Maximum Ratings*
Capacitance*
TA=25°C, VCC=3.3V±0.3V, VSS=0V Max. Unit 5 7 7 pF pF pF
Symbol Parameter Operating Temperature, TA (ambient) .....0°C to +70°C CIN1 Address Input ............ (extended)..-25°C to + 85°C CIN2 Storage Temperature(plastic)...-55°C to +150°C RAS , CAS ,, WE , OE Voltage Relative to VSS......-0.5V to + 4.6V COUT Data Input/Output Short Circuit Output Current.......20mA Power Dissipation.....1.0W
*Note: Operation above Absolute Maximum Ratings can aversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l l
All voltages are referenced to GND. After power up, wait more than 200µs and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
WE CAS DATA-IN BUFFER 4 DQ0 DQ1 DQ2 DQ3
NO.2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
OE COLUMNADDRESS BUFFER 10 COLUMN DECODER 1024 REFRESH CONTROLLER SENSE AMPLIFIERS I/O GATING 4
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10
REFRESH COUNTER
1024
ROW ADDRESS BUFFERS
ROW DECODER
10
1024
1024 x 1024 x 4 MEMORY ARRAY
RAS
NO.1 CLOCK GENERATOR
VDD VSS
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F,No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Tawian.
-3-
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