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Details, datasheet, quote on part number:GS7005-CQT
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Datasheet text preview:
352/,1; TM GS7005
C omp l et e Serial Digital Video Receiver
DATA SHEET FE ATURE S · SMPTE 259M-C compliant · fully integrated 270 Mb/s SDI receiver · integrated cable equalization (100m Belden 8281 typical) · low power consumption (750mW typical) · operates from 0°C to 85°C · small footprint with minimal external components · Lock and Carrier Detect output indications · H timing signal output · SMPTE descrambler and NRZI decoder may be disabled for DVB - ASI applications · ease of design use and adjustment free operation ORDERING O RDE RI N G INFORMATION APP LI CATI O N S Limited space, low power SMPTE 259M-C or generic 270Mb/s serial to parallel interfaces; DVB-ASI 270Mb/s receive interface; broadcast quality uncompressed video interface for industrial and professional video equipment such as video editing workstations.
PART NUMBER PACKAGE TEMPERATURE
D E S C R I P TI O N The GS7005 is a BiCMOS integrated circuit capable of operating as a complete 270Mb/s Serial Digital Video receiver. The GS7005 provides a complete serial digital video receive solution while consuming only 750mW. The serial data input accepts SMPTE 259M-C compliant signals. An on-chip by-passable equalizer typically provides 100m of co-axial cable equalization. The clock recovery is performed on chip with minimal external components. The incoming serial data is decoded using an NRZI decoder and SMPTE descrambler to provide SMPTE 125M compliant 27Mb/s parallel data outputs and clock.
GS7005
GS7005 - CQT GS7005 - CTT
52 pin MQFP 52 pin MQFP Tape
0°C to 85°C 0°C to 85°C
C1 C2
LOCK CD
SIGNAL LOCK DETECT
PLL
f/10 PCLKOUT H
MUX
TRS DETECTOR SDI SDI EQUALIZER SLICER NRZI DECODER DESCRAMBLER
S to P 10
DOUT[9:0}
EQ
SMPTE
BLOCK DIAGRAM
Revision Date: July 2001 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com
Document No. 522 - 14 - 07
ABS O LUTE MAXIMUM RATINGS
PARAMETER VALUE
Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation (VCC = 5.25V) Maximum Die Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10s)
5.5V GND < VIN < VCC 10mA
GS7005
1W 125°C 0°C <= TA <= 85°C -65°C <= TS <= 150°C 260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25°C, unless otherwise specified. Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, PCLK = 27MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TY P
MAX
UNITS
NOTES
TEST LEVEL
Positive Supply Voltage
VCC P
ICC
Operating range VCC = 5.25V VCC = 5.25V VCC = 5.25V VCC = 4.75V VCC = 5.25V VCC = 4.75V
4.75
5.00
5.25
V
6
Power Consumption Supply Current Logic Inputs - Low Logic Inputs - High Logic Outputs - Low Logic Outputs - High
2 2.4
750 140 -
0.8 0.5 -
mW mA V V V V
5 1 6 6 1 1
VIL VIH VOL VOH
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
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GENNUM CORPORATION 522 - 14 - 07
AC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25°C, unless otherwise specified in `conditions' Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, PCLK = 27MHz
PARAMETER
SYMBOL
CONDITIONS
MI N
TYP
MAX
UNITS
NOTE S
TEST LEVEL
Parallel Data - Rise/Fall Time PCLK Rising Edge to DOUT(N) Centre PCLK Rise/Fall Time Input Return Loss
tR/F_DOUT tD tR/F_PCLKOUT LOSSIN
CL = 20pF
1.0 -
17
6.0 ±5 3.0 -
ns ns ns dB
1 2, 3 1
4, 7 4, 7 4, 7 7
GS7005
CL = 20pF 75 match 5MHz to 270MHz
0.5 -
Asynchronous Lock Time Synchronous Lock Time Input Jitter Tolerance Output PCLK Jitter
tLOCK_ASYNC tLOCK_SYNC tJ_SI tJ_PCLKOUT Pathological Input Pseudorandom Input Pathological Input
-
0.35 800
250 10 -
ms µs U.I. ps p-p
4 5 6
1 1 7 1
-
1000 100
-
ps p-p m
6
7 7
Error Free Cable Length
Pseudorandom Input Pathological Input
75
100
-
m
6, 7
1
NOTES 1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the specified value. 2. Refer also to Figure 10. 3. This is the time difference between the rising edge of PCLKOUT and the centre of the bit period. 4. This is the time delay between a valid serial TRS signal on the input to the moment valid data appears on the parallel outputs. 5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned. 6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3. 7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75 connections. The MIN value is fully tested and the TYP value is based on using the EB7005 Evaluation Board. TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
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GENNUM CORPORATION 522 - 14 - 07
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