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Part: GS9023A
Category:
Multimedia
-> Video
-> Video Transport
Description: SD Embedded Audio Codec
Company: Gennum Corporation
Datasheet: Download GS9023A datasheet File size : 28 kB
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Datasheet text preview:
GENLINX TMII GS9023A
Embedded Audio CODEC
DATA SHEET FEATURES · single chip embedded audio solution · operates as an embedded audio multiplexer or demultiplexer · full support for 48kHz synchronous 20/24 bit audio · 4 channels of audio per GS9023A · cascadable architecture supports additional audio channels · multiplexes and demultiplexes arbitrary ANC data packets · support for 143, 177, 270, 360 and 540 Mb/s video standards · full processing of audio parity, channel status and user data · multiplexes and demultiplexes audio control packets · EDH generation and insertion when in Multiplex Mode · 3.3V core with 3.3V or 5V I/O (requires 5V supply) · complies with SMPTE 272M A, B, and C APPLICATIONS SDI Embedded Audio ORDERING INFORMATION
PART NUMBER G S 9023AC FY PACKAGE 100 pin LQFP TEMPERATURE 0°C to 70°C
DESCRIPTION The GS9023A is a highly integrated, single chip solution for the multiplexing/demultiplexing of digital audio channels into and out of digital video signals. The GS9023A supports the multiplexing/demultiplexing of 20 or 24-bit synchronous audio data with a 48kHz sample rate. Audio signals with different sample rates may be sample rate converted to 48kHz before and after the GS9023A using audio sample rate converters. Each GS9023A supports all the processing required to handle the multiplexing/demultiplexing of four digital audio channels. To simplify system design, the GS9023A seamlessly integrates with common AES/EBU digital audio receivers and transmitters. The cascadable architecture allows for the multiplexing/demultiplexing of additional audio channels with no external glue logic. The GS9023A supports video standards with rates from 143Mb/s to 540Mb/s. When in Multiplex Mode, the GS9023A supports the generation and insertion of EDH information according to SMPTE RP165. In combination with Gennum's GS9032, the GS9023A provides a low power, highly integrated two chip solution for SDI transmit applications. In combination with Gennum's GS7005, the GS9023A provides a low power, highly integrated two chip solution for SDI receive applications. The GS9023A requires a 3.3V power supply for internal core logic and a 3.3V or 5V power supply for device I/O.
GS9023A
WCINA/B AINA/B AUXEN
2 3 Convert Input Data Format Convert AES/EBU Format
MPX
S/P 10
MPX MPX 10 10 10 Audio Buffer 10 MPX
AM[2:0] SAFA/B CSA/B UDA/B VFLA/B MUTE ADDR[3:0] CS, WE, RE DATA[7:0] DIN[9:0] VM[2:0]
3 Convert Control Code
8
Add CRC 10 MPX Generate Audio Packets 8 Arbitrary Packet Buffer
Add EDH
10 DOUT[9:0]
7 8 10 3 Control Registers
9 b9=b8
10
Video Detection & Synchronization
Generate ANCI area 9 LOCK PKT[8:0] EDH_INS
MULTIPLEX MODE BLOCK DIAGRAM
Revision Date: May 2003 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 19795-4
TRS
GS9023A
ANCI DIN[9:0] 10 Video Detection & Synchronization
Delete ANCI 10
Delete TRS
10
DOUT[9:0]
Detect ANCI 10 Output Arbitrary Packet Output Control Code
3
LOCK BUFERR AUXEN PKT[8:0] SAFA/B CSA/B UDA/B VFLA/B WCOUT
9
8
Audio Buffer Control Registers
10
P/S
Add CRC
Convert Output Data Format Convert AES/EBU Format 3 AM[2:0]
2
AOUTA/B
7
8
ADDR[3:0], CS, WE, RE
DATA[7:0]
MUTE
DEMULTIPLEX MODE BLOCK DIAGRAM
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GENNUM CORPORATION
19795-4
PIN CONNECTIONS
TEST DATA2 DATA1 DATA0 GND BUFERR NC LOCK VDDIO D OUT0 D OUT1 D OUT2 D OUT3 D OUT4 D OUT5 D OUT6 D OUT7 GND D OUT8 D OUT9 A OUTA A OUTB WC OUT NC VDDIO
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 GS9023A 38 88 37 89 (TOP VIEW) 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDDIO DATA3 DATA4 DATA5 DATA6 DATA7 GND RE WE CS ADDR3 ADDR2 ADDR1 ADDR0 VDDINT ANCI TRS EDH_INS MUTE AM2 AM1 AM0 GND ACLK GND
GND PKTEN PKT0 PKT1 PKT2 PKT3 PKT4 PKT5 PKT6 PKT7 PKT8 VDDIO AUXEN CSB CSA UDB UDA VFLB VFLA SAFB SAFA GND TEST TEST VDDINT
GS9023A
PIN DESCRIPTIONS
NUMBER 1, 17, 26, 90 2-4 SYMBOL VDDINT VM[2:0] I TYPE DESCRIPTION +3.3V power supply pins for core logic. Video standard format. Used in conjunction with the TRS pin. VM[2] is the MSB and VM[0] is the LSB. See Table 1. Mode of operation. When set HIGH, the GS9023A operates in Demultiplex Mode. When set LOW, the GS9023A operates in Multiplex Mode. NOTE: A device reset must be performed when switching between Multiplex and Demultiplex Modes while the device is powered up. 6-10, 12-16 DIN[9:0] I Parallel digital video signal input. DIN[9] is the MSB and DIN[0] is the LSB. The digital video input must contain TRS information. 11, 23, 25, 29, 50, 58, 71, 82, 98, 100 18 G ND Device ground.
5
DE M U X / M U X
RESET
19
WCINA
VDDINT VM2 VM1 VM0 DEMUX/MUX DIN9 DIN8 DIN7 DIN6 DIN5 GND DIN4 DIN3 DIN2 DIN1 DIN0 VDDINT
NOTE: The GS9023A DOUT[9:0] MSB to LSB convention is compatible with the GS9022 but reversed with the GS9032 or GS7005. See Interconnection with GS9032 or GS7005 section.
I
I
Device reset. Active low. NOTE: The video input to output data path will be interrupted during device reset.
I
48kHz word clock for channels 1 and 2. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode.
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GENNUM CORPORATION
RESET WC INA WC INB A INA A INB GND PCLK GND
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