|
Details, datasheet, quote on part number:74116A
| |
Datasheet text preview:
G S 7 4 1 1 6 A T P / J /X SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features
· Fast access time: 6, 7, 8, 10, 12 ns · CMOS low power operation: 170/150/130/105/95 mA at minimum cycle time · Single 3.3 V power supply · All inputs and outputs are TTL-compatible · Byte control · Fully static operation · Industrial Temperature Option: 40° to 85°C · Package line up J: 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package X: 6 mm x 10 mm Fine Pitch Ball Grid Array package
256K x 16 4Mb Asynchronous SRAM
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 V DD V SS DQ5 DQ6 DQ7 DQ8 WE A 15 A 14 A 13 A12 A 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
6, 7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS
SOJ 256K x 16-Pin Configuration (Package J)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB D Q 16 D Q 15 D Q 14 D Q 13 VSS VDD D Q 12 D Q 11 D Q 10 DQ9 NC A8 A9 A10 A11 A 17
Top view
44-pin SOJ
Description
The GS74116A is a high speed CMOS Static RAM organized as 262,144 words by 16 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS74116A is available in a 6 x 10 mm Fine Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions Symbol
A0A17 DQ1DQ16 CE LB UB WE OE VDD VSS NC
FP-BGA 256K x 16 Bump Configuration (Package X) Description
Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect
A B C D E F G H LB DQ16 OE UB A0 A3 A5 A17 NC A8 A10 A13 A1 A4 A6 A7 A16 A9 A11 A14 A2 CE DQ2 DQ4 DQ5 DQ7 WE A15 NC DQ1 DQ3 VDD VSS DQ6 DQ8 NC 1 2 3 4 5 6
DQ14 DQ15 VSS VDD DQ13 DQ12
DQ11 DQ10 DQ9 NC NC A12
6 x 10 mm Bump Pitch Rev: 1.02 3/2002 1/15 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 7 4 1 1 6 A T P / J /X
Top View
TSOP-II 256K x 16 Pin Configuration (Package TP)
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 V DD V SS DQ5 DQ6 DQ7 DQ8 WE A 15 A14 A 13 A12 A 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB D Q 16 D Q 15 D Q 14 D Q 13 V SS V DD D Q 12 D Q 11 D Q 10 DQ9 NC A8 A9 A 10 A 11 A17
Top view
44 pin TSOP II
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A 17 CE WE Control OE _____ UB LB _____
Column Decoder
I/O Buffer
DQ1
DQ16
Rev: 1.02 3/2002
2/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 7 4 1 1 6 A T P / J /X
Truth Table CE
H
OE
X
WE
X
LB
X L
UB
X L H L L H L X H
DQ1 to DQ8
Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z
DQ9 to DQ16
Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z
VDD Current
ISB1, ISB2
L
L
H
L H L
L
X
L
L H
ID D
L L
H X
H X
X H
Note: X: "H" or "L"
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
VDD V IN VOUT PD T STG
Rating
0.5 to +4.6 0.5 to VDD +0.5 (£ 4.6 V max.) 0.5 to VDD +0.5 (£ 4.6 V max.) 0.7 55 to 150
Unit
V V V W
oC
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.02 3/2002
3/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 7 4 1 1 6 A T P / J /X Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12 Supply Voltage for -6 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
V DD V DD VIH VIL TAc T AI
Min
3.0 3.135 2.0 0.3 0 40
Typ
3.3 3.3 -- -- -- --
Max
3.6 3.6 VDD +0.3 0.8 70 85
Unit
V V V V
o
C C
o
Note: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance Output Capacitance
Symbol
C IN COUT
Test Condition
VIN = 0 V VOUT = 0 V
Max
5 7
Unit
pF pF
Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
II L IL O VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = 4 mA ILO = +4 mA
Min
1 uA 1 uA 2.4 --
Max
1 uA 1 uA -- 0.4 V
Rev: 1.02 3/2002
4/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 7 4 1 1 6 A T P / J /X
Power Supply Currents
Parameter Symbol Test Conditions CE £ VIL All other inputs S VIH or £ VIL Min. cycle time IOUT = 0 mA CE S VIH All other inputs S VIH or £VIL Min. cycle time CE S VDD - 0.2V All other inputs S VDD - 0.2V or £ 0.2V 0 to 70°C 6 ns 7 ns 8 ns 10 ns 12 ns 6 ns 7 ns 40 to 85°C 8 ns 10 ns 12 ns Unit
Operating Supply Current
ID D
170
150
130
105
90
180
160
140
115
100
mA
Standby Current
IS B 1
40
40
30
25
25
50
50
40
35
35
mA
Standby Current
IS B 2
10
20
mA
AC Test Conditions
Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2
Output Load 1
DQ 50W VT = 1.4 V 30pF1
Output Load 2
3.3 V DQ 5pF1 589W 434W
Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.02 3/2002
5/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
