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Part: 82032A
Category:
Memory
-> SRAM
-> 2 Mb
-> Burst SRAM
Description: Synchronous Burst SRAMs, 2Meg, 64K X 32,3.3 V
Company: GSI Technology
Datasheet: Download 82032A datasheet File size : 78 kB
Request For quote: Find where to buy 82032A
Datasheet text preview:
GS82032AT/Q-200/180/166/133/100 TQFP, QFP Commercial Temp Industrial Temp Features
· FT pin for user-configurable flow through or pipelined operation · Single Cycle Deselect (SCD) operation · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to Interleaved Pipelined mode · Byte Write (BW) and/or Global Write (GW) operation · Common data inputs and data outputs · Clock Control, registered, address, data, and control · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC standard 100-lead TQFP or QFP package -200 -180 -166 -133 Pipeline tCycle 5 ns 5.5 ns 6 ns 7.5 ns 3-1-1-1 tK Q 3 ns 3.2 ns 3.5 ns 4 ns IDD 170 mA 155 mA 140 mA 115 mA Flow tCycle 8.8 ns 9.1 ns 10 ns 12 ns Through tKQ 7.5 ns 8 ns 8.5 ns 10 ns 2-1-1-1 IDD 100 mA 100 mA 90 mA 80 mA -100 10 ns 5 ns 90 mA 15 ns 12 ns 65 mA
64K x 32 2M Synchronous Burst SRAM
Flow Through/Pipeline Reads
200 MHz100 MHz 7.5 ns12 ns 3.3 V VDD 3.3 V and 2.5 V I/O
The function of the Data Output Register can be controlled by the user via the FT mode pin (Pin 14 in the TQFP). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS82032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Rev: 1.08 2/2001 1/23 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 8 2 0 3 2 A T/Q- 2 0 0 / 1 8 0 / 1 6 6 / 1 3 3 / 1 0 0
GS82032A 100-Pin TQFP and QFP Pinout
NC D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 VSS VDDQ DQC2 D Q C1 FT VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS V DDQ D Q D7 D Q D8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 64K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
NC DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 NC
Rev: 1.08 2/2001
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS V DD NC NC A10 A11 A12 A13 A14 A15 NC 2/23 © 2000, Giga Semiconductor, Inc.
G S 8 2 0 3 2 A T/Q- 2 0 0 / 1 8 0 / 1 6 6 / 1 3 3 / 1 0 0
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 87 93, 94 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
Symbol
A0, A1 A2A15 DQA1DQA8 DQB1DQB8 DQC1DQC8 DQD1DQD8 NC BW BA, BB BC, BD CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ
Type
I I
Description
Address field LSBs and Address Counter preset Inputs Address Inputs
I/O
Data Input and Output pins No Connect
I I I I I I I I I I I I I I I I
Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply
Rev: 1.08 2/2001
3/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 8 2 0 3 2 A T/Q- 2 0 0 / 1 8 0 / 1 6 6 / 1 3 3 / 1 0 0
GS82032A Block Diagram
A0A n
Register
D
Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q D
Register
D BB
Q
32 4
32
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
D
Q
Register
E1 E2 E3
D
Q
Register
D
Q
FT G Power Down Control D Q x 1 D Q x 8
ZZ
Rev: 1.08 2/2001
4/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
G S 8 2 0 3 2 A T/Q- 2 0 0 / 1 8 0 / 1 6 6 / 1 3 3 / 1 0 0
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
L H or NC L H or NC L or NC H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
Note: There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10 1st address 2nd address 3rd address 4th address
Interleaved Burst Sequence
A[1:0] 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table Function
Read Read Write byte A Write byte B Write byte C Write byte D Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.08 2/2001
5/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Others parts begin by 82
82-1 82-2
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