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Details, datasheet, quote on part number:820V32
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Datasheet text preview:
GSI TECHNOLOGY
GS820V32Q/T 4/5/6, 2.5V I/O, 2.0mA Features
· Single 3.3V +5%/-5% power supply · Separate VDDQ to allow 2.375V to 3.465V output supply level · High frequency operation: 117MHz · Fast access time: 4.5ns Clock to Q · Low power: 0.5mA ISB and IDD static · FT mode pin for either flow-thru or pipeline operation · LBO mode pin for linear or interleave (PentiumTM and X86)
burst mode
GS820V32Q/T
80-133MHz (P/L) 66MHz Flow-Thru
64K x 32 Burst
· Byte write (BWE) and global write (GW) operation · 3 chip enable signals for easy depth expansion · 2 cycles enable (pipeline mode) and 1 cycle disable to allow multiple
bank without data buss contention
· Compatible to both 3.3V and 2.5V interface level · Standard Industrial Temperature Option: -40 to +85C · JEDEC standard 100 lead package:
Q: QFP T: TQFP
Pentium is a trademark of Intel Corp.
Functional Description
The GS820V32 is a 64Kx32 high performance synchronous SRAM with 2 bit burst counter. It is designed to provide L2 Cache for PentiumTM and other high performance CPU. Addresses (A0-15), data IOs (DQ1-32), chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV) and write control inputs (BW1, BW2, BW3, BW4, BWE, GW) are synchronous and are controlled by a positive edge triggered clock (CLK).
Output enable (OE) and power down control (ZZ) are asynchronous. 2 mode control pins (LBO & FT) define 4 operation modes of linear/interleave burst order and output flow-thru/pipeline. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst address are generated internally and are controlled by ADV. The burst sequence is either interleave order (PentiumTM and X86) or linear order and is defined by LBO. Output registers are provided and are controlled by FT mode pin. With FT mode pin, Output registers can be programmed in either pipeline mode for very high frequency operation (117MHz) or flow-thru mode for reduced latency. Byte write operation can be obtained through byte write enable (BWE) input combined with 4 individual byte write signals BW1-4. In addition, global write (GW) signal is also available to write all bytes at once. Low power state (standby mode) can be obtained either through the assertion of ZZ signal or simply stop the clock (CLK). In standby mode, memory data are still retained. Low power design of 0.5mA standby are provided on L version. The GS820V32 operates from a 3.3V power supply and all inputs and outputs are LVTTL compatible. Separate output power (VDDQ) and ground (VSSQ) pins are employed to decouple output noise from internal circuit and VDDQ allow user the flexibility to employ lower output supply level like 2.5V. GS820V32's interface level is also compatble to 2.5V supply level. The GS820V32 is implemented with GSI's high performance CMOS technology and is available in JEDEC standard 100 lead QFP ( Q version ) and TQFP ( T version) package.
Pin configuration
Top view
A6 A7 CE 1 CE 2 BW 4 B W3 BW 2 B W1 CE3 VDD V SS CL K GW BW E OE A D SC A D SP A DV A8 A9
A0-15 CLK BWE BW1,BW2 BW3,BW4 GW CE1,CE2, CE3 OE ADV ADSP, ADSC DQ1-32 ZZ FT LBO VDD VSS VDDQ VSSQ NC
Address Inputs Clock Input Byte Write Enable Byte Write. BW1 for DQ1-8; BW2 for DQ9-16; BW3 for DQ17-24; BW4 for DQ25-32 Global Write Enable Chip Enable Output Enable Burst Address advance Address Status Data I/O Power down control Flow-Thru mode Linear Burst mode 3.3V Power Supply Ground Output Power (3.465Vmax) Output Ground No Connect Supply, 2.375V to VDD
NC DQ17 DQ18 VDDQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VDDQ DQ23 DQ24 FT VDD NC VSS DQ25 DQ26 VDDQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VDDQ DQ31 DQ32 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 80 1 DQ16 79 2 DQ15 78 3 VDDQ 77 4 VSSQ 76 5 DQ14 75 6 DQ13 74 7 DQ12 73 8 DQ11 72 9 71 10 VSSQ 70 11 VDDQ 69 12 DQ10 68 13 DQ9 67 14 VSS 66 15 NC 65 VDD 16 64 ZZ 17 63 DQ8 18 DQ7 62 19 61 20 VDDQ 60 21 VSSQ 59 22 DQ6 58 23 DQ5 57 24 DQ4 56 25 DQ3 55 VSSQ 26 54 VDDQ 27 53 DQ2 28 52 DQ1 29 51 NC 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 pin QFP / TQFP
Rev. 9/09/97
L BO A5 A4 A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A 12 A13 A14 A15 NC
1/15
GSI TECHNOLOGY
GS820V32Q/T 4/5/6, 2.5V I/O, 2.0mA
Functional Block Diagram
16 A0-15 Register D Q A0 D0 A1 D1 Binary Counter Q1 A Q0 A0 A1 16
GS820V32Q/T
80-133MHz (P/L) 66MHz Flow-Thru
64K x 32 Burst
Load LBO ADV CLK ADSC ADSP GW BWE BW1 Register D Q
64Kx32 Memory Array
Q D
Register D Q BW2 Register D Q BW3
32 4
32
Register Q D
Register D Q BW4
Register D Q
CE1 CE2 CE3
Register D Q
Register D Q
FT OE Powerdown Control
Register Q D 32 DQ1-32
ZZ
Rev. 9/09/97
2/15
GSI TECHNOLOGY
GS820V32Q/T 4/5/6, 2.5V I/O, 2.0mA
GS820V32Q/T
80-133MHz (P/L) 66MHz Flow-Thru
64K x 32 Burst
Mode pin function Function Linear Burst Interleaved Burst FT L H or NC Function
LBO L H or NC
Flow-Thru Pipeline
Power down control ZZ L or NC H Function Active Standby IDD=ISB
Note: There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Linear Burst sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
The burst wrap around to initial state upon completion
The burst wrap around to initial state upon completion
Byte Write Function Function Read Read Write all bytes Write all bytes Write byte 1 Write byte 2 Write byte 3 Write byte 4
Note: H=logic high, L=logic low, NC= no connect
SGW BWE BW1 BW2 BW3 BW4 H H L H H H H H H L X L L L L L X H X L L H H H X H X L H L H H X H X L H H L H X H X L H H H L
Rev. 9/09/97
3/15
GSI TECHNOLOGY
GS820V32Q/T 4/5/6, 2.5V I/O, 2.0mA
GS820V32Q/T
80-133MHz (P/L) 66MHz Flow-Thru
64K x 32 Burst
Synchronous truth table Address used CE1 none none none none none external external next next current current external next next current current H L L L L L L X H X H L X H X H CE2 X L X L X H H X X X X H X X X X X X H X H L L X X X X L X X X X X X X L L L H H X H X H H X H X L L L X X X L H H H H L H H H H X X X X X X X L L H H X L L H H
Cycle Deselect Deselect Deselect Deselect Deselect Read, begin burst Read, begin burst Read, continue burst Read, continue burst Read, suspend burst Read, suspend burst Write, begin burst Write, continue burst Write, continue burst Write, suspend burst Write, suspend burst
Note:
CE3 ADSP ADSC ADV BWx X X X X X X H H H H H L L L L L
1. X=don't care, H=logic high, L=logic low 2. BWx is the logic function of GW, BWE, BW1, BW2, BW3, BW4. See Byte Write Function table for detail. 3. All inputs in the table must meet setup and hold on rising edge of CLK.
DQ Bus Control and Asynchronous OE Cycle Read Read Write Deselect OE L H X X DQ Q Hi-Z Hi-Z; D Hi-Z
Note: On the write cycle that follows read cycle, OE need to be held high prior to the start of write cycle to tri-state DQ buss and allow data input to SRAM.
Rev. 9/09/97
4/15
GSI TECHNOLOGY
GS820V32Q/T 4/5/6, 2.5V I/O, 2.0mA
GS820V32Q/T
80-133MHz (P/L) 66MHz Flow-Thru
64K x 32 Burst
Parameter Symbol VDD VDDQ VCLK VIN VOUT PD Topr Tstg Rating -0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDD+0.5 ( 4.6 V max. ) -0.5 to VDD+0.5 ( 4.6 V max. ) 1.5 0 to 70 -55 to 150 V V V V V
Absolute Maximum Ratings (Voltage reference to VSS=0V) Unit
Supply Voltage Output Supply Voltage CLK Input Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
W
o
C C
o
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions (Voltage reference to VSS=0V) (VDD=3.135V to 3.465V, Ta=0 70C) Parameter Supply Voltage Output Supply Voltage Input High Voltage Input Low Voltage Symbol VDD VDDQ VIH VIL Min. 3.135 2.375 1.7 -0.3 Typ. 3.3 3.3 ----Max. 3.465 3.465 VDD+0.3 0.8 Unit V V V V
Note: Input overshoot voltage should be less than VDD+2V and not exceed 5ns. Input undershoot voltage should be higher than -2V and not exceed 5ns.
Capacitance ( Ta=25C, f=1MHz) Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test conditions VIN=0V VOUT=0V Typ. 4 6 Max. 5 7 Unit pF pF
Note: These parameters are sampled and are not 100% tested.
Rev. 9/09/97
5/15
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