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Part: 84018A
Category:
Memory
-> SRAM
-> 4 Mb
-> Burst SRAM
Description: Synchronous Burst SRAMs, 4Meg, 256K X 18,3.3 V
Company: GSI Technology
Datasheet: Download 84018A datasheet File size : 68 kB
Request For quote: Find where to buy 84018A
Datasheet text preview:
Preliminary GS84018/32/36AT/B-200/180/166/150/100 TQFP, BGA Commercial Temp Industrial Temp Features
· FT pin for user-configurable flow through or pipelined operation · Single Cycle Deselect (SCD) operation · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to Interleaved Pipelined mode · Byte Write (BW) and/or Global Write (GW) operation · Common data inputs and data outputs · Clock control, registered, address, data, and control · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC standard 100-lead TQFP or 119-Bump BGA package 200 180 166 150 100 tCycle 5.0 ns 5.5 ns 6.0 ns 6.6 ns 10 ns Pipeline tK Q 3.0 ns 3.2 ns 3.5 ns 3.8 ns 4.5 ns 3-1-1-1 IDD 205 mA 185 mA 170 mA 155 mA 105 mA Flow tK Q 7.5 ns 8 ns 8.5 ns 10 ns 12 ns Through tCycle 8.8 ns 9.1 ns 10 ns 12 ns 15 ns 2-1-1-1 IDD 115 mA 115 mA 105 mA 100 mA 80 mA
0 256K x 18, 128K x 32, 128K x 36 200MHz3.10VMHz 3 VDD 4Mb Sync Burst SRAMs 3.3 V and 2.5 V I/O
counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS84018/32/36A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Functional Description
Applications
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36A is available in a JEDEC standard 100-lead TQFP or 119-Bump BGA package.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Rev: 1.11 6/2001 1/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS84018/32/36AT/B-200/180/166/150/100
GS84018A 100-Pin TQFP Pinout
NC NC NC VDDQ V SS NC NC DQB1 DQB2 V SS V DDQ DQB3 DQB4 FT VDD NC V SS DQB5 DQB6 V DDQ VSS DQB7 DQB8 DQB9 NC VSS V DDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
A 17 NC NC V DDQ V SS NC DQA 9 DQA 8 DQA 7 V SS V DDQ DQA 6 DQA 5 V SS NC V DD ZZ DQA 4 DQA 3 V DDQ V SS DQA 2 DQA 1 NC NC V SS V DDQ NC NC NC
Rev: 1.11 6/2001
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A3 A2 A1 A0 NC NC VSS V DD NC NC A10 A11 A12 A13 A14 A15 A16 2/31 © 1999, Giga Semiconductor, Inc.
Preliminary GS84018/32/36AT/B-200/180/166/150/100
GS84032A 100-Pin TQFP Pinout
NC D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 VSS VDDQ DQC2 D Q C1 FT VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS V DDQ D Q D7 D Q D8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
NC DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 NC
Rev: 1.11 6/2001
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A3 A2 A1 A0 NC NC VSS V DD NC NC A10 A11 A12 A13 A14 A15 A16 3/31 © 1999, Giga Semiconductor, Inc.
Preliminary GS84018/32/36AT/B-200/180/166/150/100
GS84036A 100-Pin TQFP Pinout
D Q C9 D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 V SS VDDQ DQC2 D Q C1 FT VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS VDDQ D Q D7 D Q D8 D Q D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
DQB 9 DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 DQA 9
Rev: 1.11 6/2001
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A3 A2 A1 A0 NC NC VSS V DD NC NC A10 A11 A12 A13 A14 A15 A16 4/31 © 1999, Giga Semiconductor, Inc.
Preliminary GS84018/32/36AT/B-200/180/166/150/100
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 47, 48, 49, 50 80 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 51, 80, 1, 30 51, 80, 1, 30 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57 75, 78, 79 1, 2, 3, 6, 7 25, 28, 29, 30 87 93, 94 95, 96 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 16, 38, 39, 42, 43, 66
Symbol
A0, A1 A2A16 A17 DQA1DQA8 DQB1DQB8 DQC1DQC8 DQD1DQD8 DQA9, DQB9, DQC9, DQD9 NC DQA1DQA9 DQB1DQB9 NC BW BA, BB BC, BD NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS V DDQ NC
Type
I I I I/O
Description
Address field LSBs and Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input and Output pins. (x32, x36 Version)
I/O
Data Input and Output pins (x36 Version) No Connect (x32 Version)
I/O
Data Input and Output pins (x18 Version)
I I I I I I I I I I I I I I I I -
No Connect (x18 Version) Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/'s; active low Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) No Connect (x18 Version) Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect
Rev: 1.11 6/2001
5/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Others parts begin by 84
84-1 84-2
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