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Details, datasheet, quote on part number:880F32A
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Datasheet text preview:
Preliminary GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5 100-Pin TQFP Commercial Temp Industrial Temp Features
· Flow Through mode operation; Pin 14 = No Connect · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 100-lead TQFP package -5.5 Flow Through 2-1-1-1 3.3 V 2.5 V tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) 5.5 5.5 175 200 175 200 -6 6.0 6.0 165 190 165 190 -6.5 6.5 6.5 160 180 160 180 -7 7.0 7.0 150 170 150 170 -7.5 -8.5 Unit 7.5 7.5 145 165 145 165 8.5 8.5 135 150 135 150 ns ns mA mA mA mA
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
5.5 ns8.5 ns 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
option on Pin 14. Board sites for flow through Burst RAMS should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI's pipeline/flow through-configurable Burst RAMs or any vendor's flow through or configurable Burst SRAM. Boards designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, like this RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS880F18/32/36AT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS880F18/32/36AT operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin Rev: 1.01 3/2002 1/24 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
GS880F18A 100-Pin TQFP Pinout
NC NC NC VDDQ V SS NC NC DQB1 DQB2 V SS V DDQ DQB3 DQB4 NC VDD NC V SS DQB5 DQB6 V DDQ VSS DQB7 DQB8 DQB9 NC V SS V DDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
A 18 NC NC V DDQ VSSVSS NC DQA 9 DQA 8 DQA 7 V SS V DDQ DQA 6 DQA 5 V SS NC V DD ZZ DQA 4 DQA 3 V DDQ V SS DQA 2 DQA 1 NC NC V SS V DDQ NC NC NC
Rev: 1.01 3/2002
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS V DD NC A17 A10 A11 A12 A13 A14 A15 A16 2/24 © 2001, Giga Semiconductor, Inc.
Preliminary GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
GS880F32A 100-Pin TQFP Pinout
NC D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 VSS VDDQ DQC2 D Q C1 NC VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS V DDQ D Q D7 D Q D8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
NC DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 NC
Rev: 1.01 3/2002
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS V DD NC A17 A10 A11 A12 A13 A14 A15 A16 3/24 © 2001, Giga Semiconductor, Inc.
Preliminary GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
GS880F36A 100-Pin TQFP Pinout
D Q C9 D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 V SS VDDQ DQC2 D Q C1 NC VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS VDDQ D Q D7 D Q D8 D Q D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
DQB 9 DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 DQA 9
Rev: 1.01 3/2002
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS V DD NC A17 A10 A11 A12 A13 A14 A15 A16 4/24 © 2001, Giga Semiconductor, Inc.
Preliminary GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 80 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 51, 80, 1, 30 16, 38, 39, 42, 66 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30, 95, 96, 42 87 93, 94 95, 96 89 88 98 86 83 84, 85 64 31 15, 41, 65, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
Symbol
A0, A1 A2A17 A 18 DQA1DQA8 DQB1DQB8 DQC1DQC8 DQD1DQD8 DQA9, DQB9, DQC9, DQD9 NC DQA1DQA9 DQB1DQB9 NC BW BA, BB BC, BD CK GW E1 G ADV ADSP, ADSC ZZ LBO VDD VSS V DDQ
Type
I I I I/O
Description
Address field LSBs and Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input and Output pins (x36 Version)
I/O -- I/O
Data Input and Output pins (x36 Version) No Connect (x32, x36 Version) Data Input and Output pins (x18 Version)
-- I I I I I I I I I I I I I I
No Connect (x18 Version) Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low (x36 Version) Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply
Rev: 1.01 3/2002
5/24
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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