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Details, datasheet, quote on part number:880Z18
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Datasheet text preview:
Preliminary GS880Z18/36T-11/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp Features
· 512K x 18 and 256K x 36 configurations · User configurable Pipeline and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization · Fully pin compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · Pin compatible with 2M, 4M and 16M (future) devices · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleave Burst mode · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · Clock Control, registered address, data, and control · ZZ Pin for automatic power-down · JEDEC-standard 100-lead TQFP package
8Mb Pipelined and Flow Through 100 MHz66 MHz 3.3 V V D D Synchronous NBT SRAMs 2.5 V and 3.3 V VDDQ
late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS880Z18/36T may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS880Z18/36T is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package.
-11 Pipeline 3-1-1-1 Flow Through 2-1-1-1 tCycle tKQ IDD tKQ tCycle IDD 10 ns 4.5 ns 210 mA 11 ns 15 ns 150 mA
-100 10 ns 4.5 ns 210 mA 12 ns 15 ns 150 mA
-80 12.5 ns 4.8 ns 190 mA 14 ns 15 ns 130 mA
-66 15 ns 5 ns 170 mA 18 ns 20 ns 130 mA
Functional Description
The GS880Z18/36T is an 8Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA 1/25
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 1.10 8/2000
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary. GS880Z18/36T-11/100/80/66 GS880Z18T Pinout
NC NC NC VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD VDD VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV NC A17 A8 A9
A18 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 2/25 © 1998, Giga Semiconductor, Inc.
Preliminary. GS880Z18/36T-11/100/80/66 GS880Z36T Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD VDD VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV NC A17 A8 A9
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 3/25 © 1998, Giga Semiconductor, Inc.
Preliminary. GS880Z18/36T-11/100/80/66 100 Pin TQFP Pin Descriptions
Pin Location
37, 36 35, 34, 33, 32, 100, 99, 83, 82, 81, 50, 49, 48, 47, 46, 45, 44 80 89 93 94 95 96 88 98 97 92 86 85 87 58, 59, 62,63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57, 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30, 95, 96 51, 52, 53, 56, 57, 58, 59, 62,63 68, 69, 72, 73, 74, 75, 78, 79, 80 1, 2, 3, 6, 7, 8, 9, 12, 13 64 14 31 15, 16, 41, 65, 91 5,10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 38, 39, 42, 43, 66, 84
Symbol
A0, A1 A2A17 A18 CK BA BB BC BD W E1 E2 E3 G ADV CKE DQA1DQA9 DQB1DQB9 NC DQA1DQA9 DQB1DQB9 DQC1DQC9 ZZ FT LBO VDD VSS VDDQ NC
Type
In In In In In In In In In In In In In In In I/O I/O I/O I/O I/O I/O In In In In In In -
Description
Burst Address Inputs; preload the burst counter Address Inputs Address Input (x18 Version Only) Clock Input Signal Byte Write signal for data inputs DQA1-DQA9; active low Byte Write signal for data inputs DQB1-DQB9; active low Byte Write signal for data inputs DQC1-DQC9; active low (x32/x36 Versions Only) Byte Write signal for data inputs DQD1-DQD9; active low (x32/x36 Versions Only) Write Enable; active low Chip Enable; active low Chip Enable; active high; for self decoded depth expansion Chip Enable; active low, for self decoded depth expansion Output Enable; active low Advance / Load--Burst address counter control pin Clock Input Buffer Enable; active low Byte A Data Input and Output pins (x18 Version Only) Byte B Data Input and Output pins (x18 Version Only) No Connect (x18 Version Only) Byte A Data Input and Output pins (x36 Versions Only) Byte B Data Input and Output pins (x36 Versions Only) Byte C Data Input and Output pins (x36 Versions Only) Byte D Data Input and Output pins (x36 Versions Only) Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low 3.3 V power supply Ground 3.3 V output power supply for noise reduction No Connect
18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1DQD9
Rev: 1.10 8/2000
4/25
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary. GS880Z18/36T-11/100/80/66
GS880Z18/36 NBT SRAM Functional Block Diagram
DQaDQn
FT
Q
Write Data
K
Register 1
D
Write Data
Write Address
Burst Counter
K
Register 2
SA1' SA0'
Data Coherency
Read, Write and
D
K
K
Control Logic
SA1 SA0
K
Write Address
Register 1
Match
Q
E1
E2
BA
BB
BC
A0A17
LBO
BD
E3
W
K
FT
ADV
CK
Rev: 1.10 8/2000
5/25
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
CKE
G
Write Drivers
Memory Array
Register 2
K
Sense Amps
K
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