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Part: 880Z36A
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 8 Mb
Description: Synchronous NBT SRAMs, 8Meg, 256K X 36,2.5 V And 3.3 V
Company: GSI Technology
Datasheet: Download 880Z36A datasheet File size : 604 kB
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Datasheet text preview:
Preliminary GS880Z18/36AT-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features
· NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · User-configurable Pipeline and Flow Through mode · LBO pin for Linear or Interleave Burst mode · Pin compatible with 2M, 4M, and 8M devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ Pin for automatic power-down · JEDEC-standard 100-lead TQFP package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2 . 5 2 . 7 3 . 0 3 . 4 3 . 8 4 . 0 ns 4 . 0 4 . 4 5 . 0 6 . 0 6 . 7 7 . 5 ns 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA
9Mb Pipelined and Flow Through Synchronous NBT SRAM
Functional Description
250 MHz133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS880Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS880Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECStandard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA 1/25
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 1.01 3/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary GS880Z18/36AT-250/225/200/166/150/133 GS880Z18AT Pinout
NC NC NC VDDQ V SS NC NC DQB1 DQB2 V SS V DDQ DQB3 DQB4 FT VDD V DD V SS DQB5 DQB6 V DDQ VSS DQB7 DQB8 DQB9 NC V SS V DDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK W CK E G ADV NC A17 A8 A9
A 18 NC NC V DDQ V SS NC DQA 9 DQA 8 DQA 7 V SS V DDQ DQA 6 DQA 5 V SS NC V DD ZZ DQA 4 DQA 3 V DDQ V SS DQA 2 DQA 1 NC NC V SS V DDQ NC NC NC
Rev: 1.01 3/2002
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 2/25 © 2001, Giga Semiconductor, Inc.
Preliminary GS880Z18/36AT-250/225/200/166/150/133 GS880Z36AT Pinout
D Q C9 D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 V SS VDDQ DQC2 D Q C1 FT VDD V DD VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS VDDQ D Q D7 D Q D8 D Q D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK W CK E G ADV NC A17 A8 A9
DQB 9 DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 DQA 9
Rev: 1.01 3/2002
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 3/25 © 2001, Giga Semiconductor, Inc.
Preliminary GS880Z18/36AT-250/225/200/166/150/133 100-Pin TQFP Pin Descriptions
Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,47, 48, 49, 50, 83 80 89 93 94 95 96 88 98 97 92 86 85 87 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57, 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30, 95, 96 68, 69, 72, 73, 74, 75, 78, 79, 80 13, 12, 9, 8, 7, 6, 3, 2, 1 64 14 31 15, 41, 65, 91 5,10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
Symbol
A0, A1 A2A17 A 18 CK BA BB BC BD W E1 E2 E3 G ADV CKE DQB1DQB9 NC
Type
In In In In In In In In In In In In In In In I/O I/O -- I/O I/O I/O I/O In In In In In In
Description
Burst Address Inputs; Preload the burst counter Address Inputs Address Input (x18 Version Only) Clock Input Signal Byte Write signal for data inputs DQA1DQA9; active low Byte Write signal for data inputs DQB1DQB9; active low Byte Write signal for data inputs DQC1DQC9; active low (x36 Version Only) Byte Write signal for data inputs DQD1DQD9; active low (x36 Version Only) Write Enable; active low Chip Enable; active low Chip Enable; Active High. For self decoded depth expansion Chip Enable; Active Low. For self decoded depth expansion Output Enable; active low Advance/Load; Burst address counter control pin Clock Input Buffer Enable; active low Byte A Data Input and Output pins (x18 Version Only) Byte B Data Input and Output pins (x18 Version Only) No Connect (x18 Version Only) Byte A Data Input and Output pins (x36 Versions Only) Byte B Data Input and Output pins (x36 Versions Only) Byte C Data Input and Output pins (x36 Versions Only) Byte D Data Input and Output pins (x36 Versions Only) Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply
58, 59, 62,63, 68, 69, 72, 73, 74 DQA1DQA9
63, 62, 59, 58, 57, 56, 53, 52, 51 DQA1DQA9 DQB1DQB9 DQC1DQC9 ZZ FT LBO V DD V SS V DDQ
18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1DQD9
Rev: 1.01 3/2002
4/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS880Z18/36AT-250/225/200/166/150/133
GS880Z18/36A NBT SRAM Functional Block Diagram
DQaDQn
FT
Q
Write Data
K
Register 1
D
Write Data
Write Address
Burst Counter
K
Register 2
SA1' SA0'
Read, Write and
Data Coherency
D
K
K
Control Logic
SA1 SA0
K
Write Address
Register 1
Match
Q
A0An
LB O
W
K
FT
BA
BB
E1
E2
ADV
E3
CK
Rev: 1.01 3/2002
5/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CKE
BC
BD
G
Write Drivers
M e mo r y Array
Register 2
K
Sense Amps
K
Others parts begin by 88
88-1
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