|
Details, datasheet, quote on part number:GS74116-10
| |
Datasheet text preview:
GS74116TP/J/U SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features
· Fast access time: 8, 10, 12, 15ns · CMOS low power operation: 170/145/130/110 mA at min.cycle time. · Single 3.3V ± 0.3V power supply · All inputs and outputs are TTL compatible · Byte control · Fully static operation · Industrial Temperature Option: -40° to 85°C · Package line up J: 400mil, 44 pin SOJ package TP: 400mil, 44 pin TSOP Type II package U: 7.20mm x 11.65mm Fine Pitch Ball Grid Array package
256K x 16 4Mb Asynchronous SRAM
SOJ 256K x 16 Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD V SS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
8, 10, 12, 15ns 3.3V VDD Center VDD & VSS
Top view
44 pin SOJ
Description
The GS74116 is a high speed CMOS static RAM organized as 262,144-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3V power supply and all inputs and outputs are TTL compatible. The GS74116 is available in a 7.2x11.65 mm Fine Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II packages.
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 A17
Pin Descriptions Symbol
A0 to A17 DQ1 to DQ16 CE LB UB WE OE V DD VSS NC
Description
Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3V power supply Ground No connect
Fine Pitch BGA 256K x 16 Bump Configuration
1 2 3 4 5 6
A B C D E F G H
LB DQ1 6
OE UB
A0 A3 A5 A17 NC A8 A10 A13
A1 A4 A6 A7 A16 A9 A11 A14
A2 CE DQ2 DQ4 DQ5 DQ7 WE A15
NC DQ1 DQ3 VDD VSS DQ6 DQ8 NC
DQ14 DQ15 VSS VDD DQ13 DQ12
DQ11 DQ10 DQ9 NC NC A12
7.2x11.65mm 0.75mm Bump Pitch Top View Rev: 2.02 3/2000 1/14 © 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
TSOP-II 256K x 16 Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ1 6 DQ1 5 DQ1 4 DQ1 3 VSS VDD DQ1 2 DQ11 DQ1 0 DQ9 NC A8 A9 A10 A11 A17
Top view
44 pin TSOP II
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A17 CE WE Control OE _____ UB LB _____
Column Decoder
I/O Buffer
DQ1
DQ16
Rev: 2.02 3/2000
2/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Truth Table CE
H
OE
X
WE
X
LB
X L
UB
X L H L L H L X H
DQ1 to DQ8
Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z
DQ9 to DQ16
Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z
VDD Current
ISB1, ISB2
L
L
H
L H L
L
X
L
L H
IDD
L L
H X
H X
X H
Note: X: "H" or "L"
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
V DD V IN VOUT PD TSTG
Rating
-0.5 to +4.6 -0.5 to VDD+0.5 ( 4.6V max.) -0.5 to VDD+0.5 ( 4.6V max.) 0.7 -55 to 150
Unit
V V V W
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 2.02 3/2000
3/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
