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Details, datasheet, quote on part number:GS74116ATP-10
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Datasheet text preview:
GS74116A TP/J/X SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features
· Fast access time: 7, 8, 10, 12 ns · CMOS low power operation: 150/130/105/95 mA at minimum cycle time · Single 3.3 V power supply · All inputs and outputs are TTL-compatible · Byte control · Fully static operation · Industrial Temperature Option: 40° to 85°C · Package line up J: 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package X: 6 mm x 10 mm Fine Pitch Ball Grid Array package
256K x 16 4Mb Asynchronous SRAM
A4 A3 A2 A1 A0 CE D Q1 D Q2 D Q3 D Q4 VDD VSS D Q5 DQ6 DQ7 D Q8 WE A 15 A 14 A 13 A 12 A 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS
SOJ 256K x 16-Pin Configuration (Package J)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB D Q16 D Q15 D Q14 D Q13 V SS VDD D Q12 DQ11 D Q10 D Q9 NC A8 A9 A 10 A11 A 17
Top view
44-pin SOJ
Description
The GS74116A is a high speed CMOS Static RAM organized as 262,144 words by 16 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS74116A is available in a 6 x 10 mm Fine Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions Symbol
A 0 A 17 D Q 1 DQ 1 6 CE LB UB WE OE VD D VS S NC
FP-BGA 256K x 16 Bump Configuration (Package X) Description
Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect 6 x 10 mm Bump Pitch
A B C D E F G H LB DQ16 OE UB A0 A3 A5 A17 NC A8 A10 A13 A1 A4 A6 A7 A16 A9 A11 A14 A2 CE DQ2 DQ4 DQ5 DQ7 WE A15 NC DQ1 DQ3 VDD VSS DQ6 DQ8 NC 1 2 3 4 5 6
DQ14 DQ15 VSS VDD DQ13 DQ12
DQ11 DQ10 DQ 9 NC NC A12
Rev: 1.03 10/2002
1/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116A TP/J/X
Top View
TSOP-II 256K x 16 Pin Configuration (Package TP)
A4 A3 A2 A1 A0 CE D Q1 D Q2 D Q3 D Q4 VDD V SS D Q5 D Q6 D Q7 D Q8 WE A 15 A14 A 13 A12 A 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 A 17
Top view
44 pin TSOP II
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A1 7 CE WE Control OE _____ UB LB _____
Column Decoder
I/O Buffer
D Q1
D Q1 6
Rev: 1.03 10/2002
2/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116A TP/J/X
Truth Table CE
H
OE
X
WE
X
LB
X L
UB
X L H L L H L X H
DQ1 to DQ8
Not Selected Read Read High Z Write Write Not Write, High Z H igh Z H igh Z
DQ9 to DQ16
Not Selected Read High Z R ead Write Not Write, High Z Write H igh Z H igh Z
VDD Current
ISB1, ISB2
L
L
H
L H L
L
X
L
L H
ID D
L L
H X
H X
X H
Note: X: "H" or "L"
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
V DD VIN V OUT PD TSTG
Rating
0.5 to +4.6 0.5 to VDD +0.5 ( 4.6 V max.) 0.5 to VDD +0.5 ( 4.6 V max.) 0.7 55 to 150
Unit
V V V W
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.03 10/2002
3/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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