|
|
Part: GS81032AT-5I
Category:
Description: 12ns 100MHz 32K X 32 1Mb Synchronous Burst SRAM
Company: GSI Technology
Datasheet: Download GS81032AT-5I datasheet File size : 181 kB
Request For quote: Find where to buy GS81032AT-5I
Datasheet text preview:
GS81032AT/Q-150/138/133/117/100/66 TQFP, QFP Commercial Temp Industrial Temp Features
· FT pin for user-configurable flow through or pipeline operation · Single Cycle Deselect (SCD) operation · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Common data inputs and data outputs · Clock Control, registered, address, data, and control · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 100-lead TQFP or QFP package -150 Pipeline t C y c l e 6.6 3-1-1-1 tK Q 3.8 ID D 270 F l o w tCycle 10.5 Through tKQ 9 2-1-1-1 ID D 170 -138 -133 7.25 7.5 4 4 245 240 15 15 9.7 10 120 120 -117 8.5 4.5 210 15 11 120 -100 10 5 180 15 12 120 -66 12.5 6 150 20 18 95 Unit ns ns mA ns ns mA
32K x 32 1M Synchronous Burst SRAM
Flow Through/Pipeline Reads
150 MHz66 MHz 9 ns18 ns 3.3 V VDD 3.3 V and 2.5 V I/O
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
SCD Pipelined Reads
The GS81032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS81032A is a 1,048,576-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS81032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Rev: 1.01 7/2001 1/23 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81032AT/Q-150/138/133/117/100/66
GS81032A 100-Pin TQFP and QFP Pinout
NC D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 VSS VDDQ DQC2 D Q C1 FT VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS V DDQ D Q D7 D Q D8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 32K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
NC DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 NC
Rev: 1.01 7/2001
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS V DD NC NC A10 A11 A12 A13 A14 NC NC 2/23 © 2000, Giga Semiconductor, Inc.
GS81032AT/Q-150/138/133/117/100/66
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30, 49 87 93, 94 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
Symbol
A0, A1 A2A14 DQA1DQA8 DQB1DQB8 DQC1DQC8 DQD1DQD8 NC BW BA, BB BC, BD CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS V DDQ
Type
I I
Description
Address field LSBs and Address Counter preset Inputs Address Inputs
I/O
Data Input and Output pins
No Connect I I I I I I I I I I I I I I I I Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and core ground Output driver power supply
Rev: 1.01 7/2001
3/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Others parts begin by gs
GS-1 GS-2 GS-3 GS-4 GS-5 GS-6 GS-7 GS-8 GS-9 GS-10 GS-11 GS-12 GS-13 GS-14 GS-15 GS-16 GS-17 GS-18 GS-19 GS-20 GS-21 GS-22 GS-23 GS-24 GS-25 GS-26 GS-27 GS-28 GS-29
|
|
|
