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Details, datasheet, quote on part number:GS8160F18T-6.5
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Datasheet text preview:
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5 100-Pin TQFP Commercial Temp Industrial Temp Features
· Flow Through mode operation; Pin 14 = No Connect · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 100-lead TQFP package -5.5 Flow Through 2-1-1-1 3.3 V 2.5 V tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) 5.5 5.5 175 200 175 200 -6 6.0 6.0 165 190 165 190 -6.5 6.5 6.5 160 180 160 180 -7 7.0 7.0 150 170 150 170 -7.5 -8.5 Unit 7.5 7.5 145 165 145 165 8.5 8.5 135 150 135 150 ns ns mA mA mA mA
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
5.5 ns8.5 ns 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
option on Pin 14. Board sites for flow through Burst RAMS should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI's pipeline/flow through-configurable Burst RAMs or any vendor's flow through or configurable Burst SRAM. Boards designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, like this RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS8160F18/32/36T is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS8160F18/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin Rev: 2.11 9/2002 1/25 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
GS8160F18 100-Pin TQFP Pinout
VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 NC VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
A 19 NC NC VDDQ VSSVS S NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 2.11 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD A 18 A 17 A10 A11 A12 A13 A14 A15 A16 2/25 © 1999, Giga Semiconductor, Inc.
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
GS8160F32 100-Pin TQFP Pinout
NC DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 NC VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC
Rev: 2.11 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD A 18 A17 A10 A11 A12 A13 A14 A15 A16 3/25 © 1999, Giga Semiconductor, Inc.
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