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Details, datasheet, quote on part number:GS8161V36AT-300I
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Datasheet text preview:
Preliminary GS8161V18A(T/D)/GS8161V3 2A(D)/GS8161V36A(T/D)
100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
Flow Through/Pipeline Reads
350 MHz150 MHz 1.8 V VDD 1.8 V I/O
Features
· IEEE 1149.1 JTAG-compatible Boundary Scan · 1.8 V +10%/10% core power supply · 1.8 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 100-pin TQFP and 165-bump BGA packages
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D) is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Functional Description
Applications
The GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D) is an 18,874,368-bit high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D) operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.
Parameter Synopsis
-350 Pipeline 3-1-1-1 tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) 1.8 2.85 395 455 4.5 4.5 270 305 -333 2.0 3.0 370 430 4.7 4.7 250 285 -300 2.2 3.3 335 390 5.0 5.0 230 270 -250 2.3 4.0 280 330 5.5 5.5 210 240 -200 2.7 5.0 230 270 6.5 6.5 185 205 -150 3.3 6.7 185 210 7.5 7.5 170 190 Unit ns ns mA mA ns ns mA mA
Flow Through 2-1-1-1
Rev: 1.00a 6/2003
1/34
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8161V18A(T/D)/GS8161V3 2A(D)/GS8161V36A(T/D)
GS8161V18A 100-Pin TQFP Pinout
VDDQ VSS NC NC DQB DQ B VSS VDDQ DQB DQ B FT VDD NC VSS DQB DQ B VDDQ VSS DQB DQ B D Q PB NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M X 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 A 18 NC NC BB BA A 17 VDD VSS CK GW BW G ADSC ADSP ADV A A
A NC NC VDDQ VSS NC DQPA DQ A DQ A VSS VDDQ DQ A DQ A VSS NC VDD ZZ DQ A DQ A VDDQ VSS DQ A DQ A NC NC VSS VDDQ NC NC NC
Rev: 1.00a 6/2003
LBO A A A A
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A 2/34 © 2003, Giga Semiconductor, Inc.
Preliminary GS8161V18A(T/D)/GS8161V3 2A(D)/GS8161V36A(T/D)
GS8161V36A 100-Pin TQFP Pinout
DQPC DQ C DQ C VDDQ VSS DQ C DQ C DQC DQ C VSS VDDQ DQC DQ C FT VDD NC VSS DQD DQ D VDDQ VSS DQD DQ D DQ D DQ D VSS VDDQ DQ D DQ D DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 A 18 BD BC BB BA A 17 VDD VSS CK GW BW G ADSC ADSP ADV A A
D Q PB DQ B DQ B VDDQ VSS DQ B DQ B DQ B DQ B VSS VDDQ DQ B DQ B VSS NC VDD ZZ DQ A DQ A VDDQ VSS DQ A DQ A DQ A DQ A VSS VDDQ DQ A DQ A DQPA
LBO A A A A A1 A0 TMS TDI VSS VDD Rev: 1.00a 6/2003 3/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TDO TCK A A A A A A A © 2003, Giga Semiconductor, Inc.
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