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Details, datasheet, quote on part number:GS8161Z18AD-250I
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Datasheet text preview:
Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp
18Mb Pipelined and Flow Through Synchronous NBT SRAM
300 MHz150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
Features
· User-configurable Pipeline and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization · Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · IEEE 1149.1 JTAG-compatible Boundary Scan · 2.5 V or 3.3 V +10%/10% core power supply · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2M, 4M, and 8M devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ pin for automatic power-down · JEDEC-standard 100-lead TQFP and 165-bump FP-BGA packages
Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) is implemented with GSI's high performance CMOS technology and is available in JEDEC-standard 100-pin TQFP and 165-bump FP-BGA packages.
-300 -250 2.5 4.0 280 330 5.5 5.5 210 240 -200 3.0 5.0 230 270 6.5 6.5 185 205 -150 3.8 6.7 185 210 7.5 7.5 170 190 Unit ns ns mA mA ns ns mA mA
Functional Description
The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
Parameter Synopsis
tKQ(x18/x36) tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) 2.5 3.3 335 390 5.0 5.0 230 270
Pipeline 3-1-1-1
Flow Through 2-1-1-1
Rev: 1.03a 5/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/36
© 2001, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) GS8161Z18AT Pinout
VDDQ VSS NC NC DQB DQ B VSS VDDQ DQB DQ B FT VDD NC VSS DQB DQ B VDDQ VSS DQB DQ B D Q PB NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 NC NC BB BA E3 VD D VSS CK W CKE G ADV A A A A
A NC NC VDDQ VSS NC DQPA DQ A DQ A VSS VDDQ DQ A DQA5 VSS NC VDD ZZ DQ A DQ A VDDQ VSS DQ A DQ A NC NC VSS VDDQ NC NC NC
Rev: 1.03a 5/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A A A A A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A 2/36 © 2001, Giga Semiconductor, Inc.
Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) GS8161Z36AT Pinout
DQPC DQ C DQ C VDDQ VSS DQ C DQ C DQC DQ C VSS VDDQ DQC DQ C FT VDD NC VSS DQD DQ D VDDQ VSS DQD DQ D DQ D DQ D VSS VDDQ DQ D DQ D DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 BD BC BB BA E3 VD D VSS CK W CKE G ADV A A A A
D Q PB DQ B DQ B VDDQ VSS DQ B DQ B DQ B DQ B VSS VDDQ DQ B DQ B VSS NC VDD ZZ DQ A DQ A VDDQ VSS DQ A DQ A DQ A DQ A VSS VDDQ DQ A DQ A DQPA
Rev: 1.03a 5/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A A A A A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A 3/36 © 2001, Giga Semiconductor, Inc.
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