|
Details, datasheet, quote on part number:GS816236AB-300
| |
Datasheet text preview:
Preliminary GS816218A(B/D)/GS8162 3 6 A ( B / D ) / G S 8 1 6 2 7 2 A ( C ) 119-, 165- & 209-Pin BGA Commercial Temp Industrial Temp Features
1M x 18, 512K x 36, 256K x 72 320.0 MHz150 MHz 5 V or 3.3 V VDD 18Mb S/DCD Sync Burst SRAMs 2.5 V or 3.3 V I/O
Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. The GS816218A(B/D)/GS816236A(B/D)/GS816272A(C) is an SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
· FT pin for user-configurable flow through or pipeline operation · Single/Dual Cycle Deselect selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for user-selectable high/low output drive · 2.5 V or 3.3 V +10%/10% core power supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to SCD x18/x36 Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 119-, 165-, and 209-bump BGA package
SCD and DCD Pipelined Reads
Functional Description
Applications
The GS816218A(B/D)/GS816236A(B/D)/GS816272A(C) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Byte Write and Global Write
FLXDriveTM
Controls
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in
The GS816218A(B/D)/GS816236A(B/D)/GS816272A(C) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-300 tKQ(x18/x36) tKQ(x72) tCycle Curr (x18) Curr (x32/x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x72) 2.5 2.8 3.3 335 390 495 5.0 5.0 230 270 345 -250 2.5 3.0 4.0 280 330 425 5.5 5.5 210 240 315 -200 3.0 3.0 5.0 230 270 345 6.5 6.5 185 205 275 -150 3.8 3.8 6.7 185 210 270 7.5 7.5 170 190 250 Unit ns ns ns mA mA mA ns ns mA mA mA
Pipeline 3-1-1-1
Flow Through 2-1-1-1
Rev: 1.03a 5/2003
1/37
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary GS816218A(B/D)/GS8162 3 6 A ( B / D ) / G S 8 1 6 2 7 2 A ( C ) GS816272A Pad Out 209 Bump BGA--Top View Package C
1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG DQG DQG DQG DQPG D QC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD D QD DQD 2 D QG D QG D QG D QG DQPC D QC DQC D QC DQC NC DQH D QH DQH D QH DQPH DQD D QD D QD DQD 3 A BC BH V SS VDDQ VS S VDDQ V SS VDDQ CK VDDQ V SS VDDQ V SS VDDQ VSS NC A T MS 4 E2 BG BD NC VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q NC A A TDI 5 ADSP NC NC NC VD D VSS VD D VSS VD D VSS VD D VSS VD D VSS VD D NC A A A 6 ADSC BW E1 G VD D ZQ MCH MCL MCL MCL FT MCL SCD ZZ VD D L BO A A1 A0 7 ADV A NC GW VD D VSS VD D VSS VD D VSS VD D VSS VD D VSS VD D NC A A A 8 E3 BB BE NC VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q NC A A T DO 9 A BF BA V SS VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q VSS NC A TCK 10 D QB D QB D QB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE D QE D QE DQE 11 D QB D QB D QB D QB DQPB D QF D QF D QF D QF NC D QA D QA D QA D QA DQPE D QE D QE D QE DQE
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.03a 5/2003
2/37
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816218A(B/D)/GS8162 3 6 A ( B / D ) / G S 8 1 6 2 7 2 A ( C ) GS816272A BGA Pin Description
Symbol
A0, A1 A DQA DQB D QC D QD DQE D QF D QG D QH BA, BB, BC,BD, BE, BF, BG,BH NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCL BW ZQ TMS TDI TDO TCK V DD V SS VD D Q I I I I O I I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs. Address Inputs
I/O
Data Input and Output pins
I -- I I I I I I I I I I I I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High Must Connect Low Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 1.03a 5/2003
3/37
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
