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Details, datasheet, quote on part number:GS816236B-250
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Datasheet text preview:
GS816218(B/D)/GS8162 3 6 ( B / D ) / G S 8 1 6 2 7 2 ( C ) 119-, 165- & 209-Pin BGA Commercial Temp Industrial Temp Features
1M x 18, 512K x 36, 256K x 72 18Mb S/DCD Sync Burst SRAMs
250 MHz133MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
· FT pin for user-configurable flow through or pipeline operation · Single/Dual Cycle Deselect selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for user-selectable high/low output drive · 2.5 V or 3.3 V +10%/10% core power supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to SCD x18/x36 Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 119-, 165-, and 209-bump BGA package
burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
Flow Through/Pipeline Reads
SCD and DCD Pipelined Reads
Pipeline 3-1-1-1 3.3 V
2.5 V Flow Through 2-1-1-1 3.3 V
tK Q tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) tK Q tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72)
-250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 n/a 275 320 n/a 5.5 5.5 175 200 n/a 175 200 n/a 255 300 n/a 250 295 n/a 6.0 6.0 165 190 n/a 165 190 n/a 230 270 350 230 265 335 6.5 6.5 160 180 225 160 180 225 200 230 300 195 225 290 7.0 7.0 150 170 115 150 170 115 185 215 270 180 210 260 7.5 7.5 145 165 210 145 165 210 165 190 245 165 185 235 8.5 8.5 135 150 185 135 150 185 mA mA mA mA mA mA ns ns mA mA mA mA mA mA
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Byte Write and Global Write
FLXDriveTM
2.5 V
Functional Description
Applications
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
Controls
The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Rev: 2.16a 12/2002
1/38
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS816218(B/D)/GS8162 3 6 ( B / D ) / G S 8 1 6 2 7 2 ( C ) GS816272 Pad Out 209 Bump BGA--Top View Package C
1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG5 DQG6 DQG7 DQG8 DQG9 DQC4 DQC3 DQC2 DQC1 NC DQH1 DQH2 DQH3 DQH4 DQD9 DQD8 DQD7 DQD6 DQD5 2 DQG1 DQG2 DQG3 DQG4 DQC9 DQC8 DQC7 DQC6 DQC5 NC DQH5 DQH6 DQH7 DQH8 DQH9 DQD4 DQD3 DQD2 DQD1 3 A15 BC BH V SS VD D Q VS S VD D Q V SS VD D Q CK VD D Q VS S VD D Q VS S VD D Q VS S NC A9 T MS 4 E2 BG BD NC VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q NC A14 A8 TDI 5 ADSP NC NC NC VD D VSS VD D VSS VD D VSS VD D VSS VD D VSS VD D NC A13 A7 A3 6 ADSC BW E1 G VD D ZQ MCH MCL MCL MCL FT MCL SCD ZZ VD D L BO A12 A1 A0 7 ADV A16 NC GW VD D VSS VD D VSS VD D VSS VD D VSS VD D VSS VD D NC A11 A6 A2 8 E3 BB BE NC VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q NC A10 A5 T DO 9 A17 BF BA V SS VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q VSS NC A4 TCK 10 DQB1 D QB2 D QB3 DQB4 DQF9 DQF8 DQF7 DQF6 DQF5 NC DQA5 DQA6 DQA7 DQA8 DQA9 DQE4 DQE3 D QE 2 DQE1 11 DQB5 D QB6 D QB7 DQB8 DQB9 DQF4 DQF3 DQF2 DQF1 NC DQA1 DQA2 DQA3 DQA4 DQE9 DQE8 DQE7 D QE 6 DQE5
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 2.16a 12/2002
2/38
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS8162 3 6 ( B / D ) / G S 8 1 6 2 7 2 ( C ) GS816272 BGA Pin Description
Symbol
A0, A1 An DQA1DQA9 DQB1DQB9 DQC1DQC9 DQD1DQD9 DQE1DQE9 DQF1DQF9 DQG1DQG9 DQH1DQH9 BA, BB, BC,BD, BE, BF, BG,BH NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCL BW ZQ TMS TDI TDO TCK V DD V SS VD D Q I I I I O I I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs. Address Inputs
I/O
Data Input and Output pins
I -- I I I I I I I I I I I I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High Must Connect Low Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 2.16a 12/2002
3/38
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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