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Details, datasheet, quote on part number:GS8162Z36D-166
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Datasheet text preview:
GS8162Z18(B/D )/GS8162Z 3 6 ( B / D ) / G S 8 1 6 2 Z 7 2 ( C ) 119, 165, & 209 BGA Commercial Temp Industrial Temp Features
· NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · User-configurable Pipeline and Flow Through mode · ZQ mode pin for user-selectable high/low output drive · IEEE 1149.1 JTAG-compatible Boundary Scan · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2M, 4M, and 8M devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ Pin for automatic power-down · JEDEC-standard 119-, 165-, or 209-Bump BGA package
18Mb Pipelined and Flow Through Synchronous NBT SRAM
250 MHz133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 & x36), or 209-bump (x72) BGA package.
Pipeline 3-1-1-1 3.3 V
2.5 V Flow Through 2-1-1-1 3.3 V
tK Q tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) tK Q tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72)
-250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 n/a 275 320 n/a 5.5 5.5 175 200 n/a 175 200 n/a 255 300 n/a 250 295 n/a 6.0 6.0 165 190 n/a 165 190 n/a 230 270 350 230 265 335 6.5 6.5 160 180 225 160 180 225 200 230 300 195 225 290 7.0 7.0 150 170 115 150 170 115 185 215 270 180 210 260 7.5 7.5 145 165 210 145 165 210 165 190 245 165 185 235 8.5 8.5 135 150 185 135 150 185 mA mA mA mA mA mA ns ns mA mA mA mA mA mA
2.5 V
Functional Description
The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power Rev: 2.19 6/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 1999, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8162Z18(B/D )/GS8162Z 3 6 ( B / D ) / G S 8 1 6 2 Z 7 2 ( C ) GS8162Z72 Pad Out 209-Bump BGA--Top View (Package C)
1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG5 DQG6 DQG7 DQG8 DQG9 DQC4 DQC3 DQC2 DQC1 NC DQH1 DQH2 DQH3 DQH4 DQD9 DQD8 DQD7 DQD6 DQD5 2 DQG1 DQG2 DQG3 DQG4 DQC9 DQC8 DQC7 DQC6 DQC5 NC DQH5 DQH6 DQH7 DQH8 DQH9 DQD4 DQD3 DQD2 DQD1 3 A13 BC BH V SS V DDQ V SS VD D Q VSS VD D Q CK VD D Q VSS V DDQ VSS V DDQ VSS NC A9 T MS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A12 A8 TDI 5 A14 NC NC NC VDD V SS VDD V SS VDD VSS VDD V SS VDD V SS VDD NC NC A7 A3 6 ADV W E1 G VDD ZQ MCH MCL MCH MCL FT MCL MCH ZZ VDD L BO A11 A1 A0 7 A15 A16 NC NC VDD V SS VD D V SS VD D V SS VDD V SS VD D V SS VDD PE NC A6 A2 8 E3 BB BE NC VDDQ V SS VDDQ V SS VDDQ NC VDDQ V SS VDDQ V SS VDDQ NC A10 A5 T DO 9 A17 BF BA V SS VDDQ V SS VDDQ V SS VDDQ NC VDDQ V SS VDDQ V SS VDDQ V SS NC A4 TCK 10 DQB1 D QB2 D QB3 DQB4 DQF9 DQF8 DQF7 DQF6 DQF5 NC DQA5 DQA6 DQA7 DQA8 DQA9 DQE4 DQE3 D QE 2 DQE1 11 DQB5 D QB6 D QB7 DQB8 DQB9 DQF4 DQF3 DQF2 DQF1 NC DQA1 DQA2 DQA3 DQA4 DQE9 DQE8 DQE7 D QE 6 DQE5
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 2.19 6/2003
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© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D )/GS8162Z 3 6 ( B / D ) / G S 8 1 6 2 Z 7 2 ( C ) GS8162Z72 BGA Pin Description
Symbol
A0, A1 An DQA1DQA9 DQB1DQB9 DQC1DQC9 DQD1DQD9 DQE1DQE9 DQF1DQF9 DQG1DQG9 DQH1DQH9 BA, BB, BC,BD, BE, BF, BG,BH NC CK W E1, E3 E2 G ZZ FT LBO MCH MCL PE ADV ZQ TMS TDI TDO TCK VD D VS S VD D Q I I I I I O I I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs
I/O
Data Input and Output pins
I -- I I I I I I I I I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Write Enable. Writes all enabled bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect Low Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) Burst Address Counter Advance Enable; active high FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 2.19 6/2003
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© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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