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Details, datasheet, quote on part number:GS8162Z72AC-250I
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Datasheet text preview:
Preliminary GS8162Z18A(B/D)/GS8162Z 36A(B/D)/GS8162Z72A(C) 119, 165, & 209 BGA Commercial Temp Industrial Temp Features
· NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · User-configurable Pipeline and Flow Through mode · ZQ mode pin for user-selectable high/low output drive · IEEE 1149.1 JTAG-compatible Boundary Scan · On-chip write parity checking; even or odd selectable · On-chip parity encoding and error detection · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2M, 4M, and 8M devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ Pin for automatic power-down · JEDEC-standard 119-, 165-, or 209-Bump BGA package
18Mb Pipelined and Flow Through Synchronous NBT SRAM
300 MHz150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8162Z18A(B/D)/36A(B/D)/72A(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8162Z18A(B/D)/36A(B/D)/72A(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165bump (x18 & x36), or 209-bump (x72) BGA package.
Functional Description
The GS8162Z18A(B/D)/36A(B/D)/72A(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
Parameter Synopsis
-300 tKQ(x18/x36) tKQ(x72) tCycle Curr (x18) Curr (x32/x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x72) 2.5 2.8 3.3 335 390 495 5.0 5.0 230 270 345 -250 2.5 3.0 4.0 280 330 425 5.5 5.5 210 240 315 -200 3.0 3.0 5.0 230 270 345 6.5 6.5 185 205 275 -150 3.8 3.8 6.7 185 210 270 7.5 7.5 170 190 250 Unit ns ns ns mA mA mA ns ns mA mA mA
Pipeline 3-1-1-1
Flow Through 2-1-1-1
Rev: 1.03a 5/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/36
© 2001, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary GS8162Z18A(B/D)/GS8162Z 36A(B/D)/GS8162Z72A(C) GS8162Z72 Pad Out 209-Bump BGA--Top View (Package C)
1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG DQG DQG DQG DQPG D QC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD D QD DQD 2 DQG D QG D QG D QG DQPC D QC D QC DQC DQC NC DQH DQH D QH DQH DQPH DQD D QD D QD DQD 3 A BC BH V SS V DDQ V SS V DDQ VSS VD D Q CK VD D Q VSS V DDQ VSS V DDQ VSS NC A T MS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A NC NC NC VDD V SS VDD V SS VDD VSS VDD V SS VDD V SS VDD NC NC A A 6 ADV W E1 G VDD ZQ MCH MCL MCH CKE FT MCL MCH ZZ VDD L BO A A1 A0 7 A A NC NC VDD V SS VD D V SS VD D V SS VDD V SS VD D V SS VDD PE NC A A 8 E3 BB BE NC VDDQ V SS VDDQ V SS VDDQ NC VDDQ V SS VDDQ V SS VDDQ NC A A T DO 9 A BF BA V SS VDDQ V SS VDDQ V SS VDDQ NC VDDQ V SS VDDQ V SS VDDQ V SS NC A TCK 10 D QB D QB D QB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE D QE D QE DQE 11 D QB D QB D QB D QB DQPB D QF D QF D QF D QF NC D QA D QA D QA D QA DQPE D QE DQE D QE DQE
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.03a 5/2003
2/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8162Z18A(B/D)/GS8162Z 36A(B/D)/GS8162Z72A(C) GS8162Z72 BGA Pin Description
Symbol
A0, A1 A D QA D QB DQC DQD D QE D QF D QG DQH BA, BB, BC,BD, BE, BF, BG,BH NC CK W E1, E3 E2 G ZZ FT LBO MCH MCL PE CKE BW ZQ TMS TDI TDO TCK VD D VS S VD D Q I I I I I I O I I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs
I/O
Data Input and Output pins
I -- I I I I I I I I I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Write Enable. Writes all enabled bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect Low Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) Clock Enable; active low Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 1.03a 5/2003
3/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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