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Details, datasheet, quote on part number:GS8171DW72AC-333I
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Datasheet text preview:
Preliminary GS8171DW36/72AC-350/333/300/250
209-Bump BGA Commercial Temp Industrial Temp
18Mb 1x1Dp HSTL I/O
Double Late Write SigmaRAMTM
250 MHz 350 MHz 1.8 V VDD 1.5 V I/O
Features
· Double Late Write mode, Pipelined Read mode · JEDEC-standard SigmaRAMTM pinout and package · 1.8 V +150/100 mV core power supply · 1.5 V HSTL Interface · ZQ controlled programmable output drive strength · Dual Cycle Deselect · Burst Read and Write option · Fully coherent read and write pipelines · Echo Clock outputs track data output drivers · Byte write operation (9-bit bytes) · 2 user-programmable chip enable inputs · IEEE 1149.1 JTAG-compliant Serial Boundary Scan · 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb, 72Mb, and 144Mb devices Key Fast Bin Specs Cycle Time Access Time Symbol tKHK H tKHQV - 350 2.86 ns 1.6 ns
Bottom View
209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array
Functional Description
Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. RAMs support pipelined reads utilizing a rising-edgetriggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.
SigmaRAM Family Overview
GS8171DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage HSTL I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems.
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR). The logical differences between the protocols employed by these RAMs mainly involve various approaches to write cueing and data transfer rates. The RAMTM family standard allows a user to implement the interface protocol best suited to the task at hand.
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Rev: 1.00 6/2003
1/31
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8171DW36/72AC-350/333/300/250 SigmaRAM Pinouts 256k x 72 Common I/O--Top View
1 A B C D E F G H J K L M N P R T U V W
· 2002.06
2 D Qg D Qg D Qg D Qg D Qc D Qc D Qc D Qc D Qc C Q2 DQh D Qh D Qh D Qh D Qh DQd D Qd D Qd DQd
3 A Bc Bh VS S VDDQ VS S VDDQ VS S VDDQ CK VDDQ VSS VDDQ VSS VDDQ VS S NC A TMS
4 E2 Bg Bd VR E F VDDQ VS S VDDQ VS S VDDQ CK VDDQ VS S VDDQ VS S VDDQ VR E F A A TDI
5 A NC NC (144M) NC VD D VS S VD D VS S VD D VS S VD D VS S VD D VS S VD D NC NC (72M) A A
6 ADV W E1 MCL VD D ZQ E P2 E P3 MCH MCL MCH MCL MCH MCL VD D MCL A A1 A0
7 A A NC NC VD D VSS VD D VS S VD D VS S VD D VS S VD D VS S VD D NC NC (36M) A A
8 E3 Bb Be VR E F VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q VR E F A A TDO
9 A Bf Ba VS S VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q VS S NC A TCK
10 DQb DQb DQb DQb DQf DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQa DQe D Qe D Qe D Qe
11 D Qb D Qb D Qb D Qb D Qb D Qf D Qf D Qf D Qf CQ1 D Qa D Qa D Qa D Qa D Qe D Qe D Qe D Qe DQe
DQg DQg DQg DQg DQg D Qc DQc DQc DQc CQ2 DQh DQh DQh DQh DQd DQd DQd D Qd D Qd
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.00 6/2003
2/31
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8171DW36/72AC-350/333/300/250
512k x 36 Common I/O--Top View
1 A B C D E F G H J K L M N P R T U V W
· 2002.06
2 NC NC NC NC DQc DQc D Qc D Qc D Qc C Q2 NC NC NC NC NC DQd D Qd DQd DQd
3 A Bc NC VS S VDDQ VS S VDDQ VS S VDDQ CK VDDQ VS S VDDQ VS S VDDQ VS S NC A TMS
4 E2 NC Bd VR E F VDDQ VS S VDDQ VS S VDDQ CK VDDQ VS S VDDQ VS S VDDQ VR E F A A TDI
5 A A NC (144M) NC VD D VS S VD D VS S VD D VS S VD D VS S VD D VS S VD D NC NC (72M) A A
6 ADV W E1 MCL VD D ZQ E P2 E P3 MCH MCL MCH MCL MCH MCL VD D MCL A A1 A0
7 A A NC NC VD D VSS VD D VS S VD D VS S VD D VS S VD D VS S VD D NC NC (36M) A A
8 E3 Bb NC VR E F VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q VR E F A A TDO
9 A NC Ba VS S VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q VS S NC A TCK
10 DQb DQb DQb DQb NC NC NC NC NC CQ1 DQa DQa DQa DQa DQa NC NC NC NC
11 D Qb D Qb D Qb D Qb DQb NC NC NC NC CQ1 D Qa D Qa D Qa D Qa NC NC NC NC NC
NC NC NC NC NC DQc DQc DQc DQc CQ2 NC NC NC NC DQd DQd DQd D Qd D Qd
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.00 6/2003
3/31
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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