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Details, datasheet, quote on part number:GS8180D18D-200I
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Datasheet text preview:
Preliminary GS8180D18D-330/300/ 2 5 0 / 2 0 0 / 1 6 7 / 1 3 3 / 1 0 0
165-Bump BGA Commercial Temp Industrial Temp Features
· Simultaneous Read and Write SigmaQuadTM Interface · JEDEC-standard pinout and package · Dual Double Data Rate interface · Byte Write controls sampled at data-in time · Burst of 4 Read and Write · 1.8 V +150/100 mV core power supply · 1.5 V or 1.8 V HSTL Interface · Pipelined read operation · Fully coherent read and write pipelines · ZQ mode pin for programmable output drive strength · IEEE 1149.1 JTAG-compliant Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb, 72Mb, and 144Mb devices - 330 -300 -250 -200 -167 -133 -100 10 ns
18Mb 2x2B4 SigmaQuad SRAM
100 MHz330 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1
tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 7.5 ns
tKHQV 1.6 ns 1.8 ns 2.1 ns 2.3 ns 2.5 ns 3.0 ns 3.0 ns
SigmaRAMTM Family Overview
GS8180D18 are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.
two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O 2x2B4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a 2x2B4 RAM is always two address pins less than the advertised index depth (e.g., the 1M x 18 has a 256K addressable index).
Clocking and Addressing Schemes A 2x2B4 SigmaQuad SRAM is a synchronous device. It employs
Rev: 2.01 5/2003
1/28
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8180D18D-330/300/ 2 5 0 / 2 0 0 / 1 6 7 / 1 3 3 / 1 0 0 1M x 18 SigmaQuad SRAM -- Top View
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) Q9 NC D11 NC Q 12 D13 VREF NC NC Q 15 NC D17 NC TCK 3 NC/SA (36Mb) D9 D 10 Q 10 Q 11 D 12 Q 13 VDDQ D 14 Q 14 D15 D 16 Q 16 Q 17 SA 4 W SA VSS VS S VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VS S VSS SA SA 5 BW1 NC SA VS S VS S VD D VD D VD D VD D VD D VS S VS S SA SA SA 6 K K NC VS S VS S VS S VS S VS S VS S VS S VS S VS S SA C C 7 NC BW0 SA VS S VS S VD D VD D VD D VD D VD D VS S VS S SA SA SA 8 R SA VS S VS S VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VS S VS S SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 MCL/SA (72Mb) NC Q7 NC D6 NC NC VR E F Q4 D3 NC Q1 NC D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. MCL = Must Connect Low 4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.01 5/2003
2/28
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8180D18D-330/300/ 2 5 0 / 2 0 0 / 1 6 7 / 1 3 3 / 1 0 0
Pin Description Table Symbol
SA NC R W B W 0 B W 1 K K C C TMS TDI TCK TDO VR E F ZQ MCL D0D17 Q0Q17 VD D VD D Q VS S
Description
Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Must Connect Low Synchronous Data Inputs Synchronous Data Outputs Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
In p u t -- Input In p u t Input In p u t In p u t In p u t In p u t Input Input Input Output Input Input -- In p u t Output Supply Supply Supply
Comments
-- -- Active Low Active Low Active Low Active High Active Low Active High Active Low -- -- -- -- -- -- -- -- -- 2.5 V Nominal 1.5 V Nominal --
Note: NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM's bandwidth in half. A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from
Rev: 2.01 5/2003
3/28
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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