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Details, datasheet, quote on part number:GS8180Q18D-200
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Datasheet text preview:
Preliminary GS8180Q18/36D-200/150/133/100
165-Bump BGA Commercial Temp Industrial Temp Features
· Simultaneous Read and Write SigmaQuadTM Interface · JEDEC-standard pinout and package · Dual Double Data Rate interface · Byte Write controls sampled at data-in time · Burst of 2 Read and Write · 1.8 V +150/100 mV core power supply · 1.5 V or 1.8 V HSTL Interface · Pipelined read operation · Fully coherent read and write pipelines · ZQ mode pin for programmable output drive strength · IEEE 1149.1 JTAG-compliant Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb 2x2B2 SigmaQuad SRAM
100 MHz200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
-200 tKHK H tKHQV 5.0 ns 2.3 ns -150 6.7 ns 2.7 ns -133 7.5 ns 3.0 ns -100 10.0 ns 3.0 ns 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1
SigmaRAMTM Family Overview
GS8180Q18/36 are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.
two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O 2x2B2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a 2x2B2 RAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512K addressable index).
Clocking and Addressing Schemes A 2x2B2 SigmaQuad SRAM is a synchronous device. It employs
Rev: 2.01 3/2003
1/29
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8180Q18/36D-200/150/133/100 1M x 18 SigmaQuad SRAM -- Top View
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) Q9 NC D11 NC Q 12 D13 VREF NC NC Q 15 NC D17 NC TCK 3 NC/SA (36Mb) D9 D 10 Q 10 Q 11 D 12 Q 13 VDDQ D 14 Q 14 D15 D 16 Q 16 Q 17 SA 4 W SA VSS VS S VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VS S VSS SA SA 5 BW1 NC SA VS S VS S VD D VD D VD D VD D VD D VS S VS S SA SA SA 6 K K SA VS S VS S VS S VS S VS S VS S VS S VS S VS S SA C C 7 NC BW0 SA VS S VS S VD D VD D VD D VD D VD D VS S VS S SA SA SA 8 R SA VS S VS S VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VS S VS S SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 MCL/SA (72Mb) NC Q7 NC D6 NC NC VR E F Q4 D3 NC Q1 NC D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. MCL = Must Connect Low 4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.01 3/2003
2/29
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8180Q18/36D-200/150/133/100 512K x 36 SigmaQuad SRAM -- Top View
1 A B C D E F G H J K L M N P R NC Q27 D27 D28 Q29 Q30 D30 NC D31 Q32 Q33 D33 D34 Q35 TDO 2 MCL/SA (288Mb) Q 18 Q 28 D 20 D29 Q 21 D 22 VREF Q 31 D32 Q 24 Q 34 D 26 D 35 TCK 3 NC/SA (72Mb) D18 D19 Q19 Q20 D 21 Q 22 VDDQ D23 Q23 D 24 D25 Q25 Q 26 SA 4 W SA VS S VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VS S VS S VD D VD D VD D VD D VD D VS S VS S SA SA SA 6 K K SA VS S VS S VS S VS S VS S VS S VS S VS S VS S SA C C 7 BW1 BW0 SA VS S VS S VD D VD D VD D VD D VD D VS S VS S SA SA SA 8 R SA VS S VS S VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VS S VS S SA SA 9 NC/SA (36Mb) D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 MCL/SA (144Mb) Q 17 Q7 D 15 D6 Q 14 D 13 VR E F Q4 D3 Q 11 Q1 D9 D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A9 for 36Mb, A3 for 72Mb, A10 for 144Mb, A2 for 288Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35. 4. MCL = Must Connect Low 5. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.01 3/2003
3/29
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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