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Details, datasheet, quote on part number:GS820H32A
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Datasheet text preview:
GS820H32AT/Q-150/138/133/117/100/66 TQFP, QFP Commercial Temp Industrial Temp Features
· FT pin for user configurable flow through or pipelined operation. · Single Cycle Deselect (SCD) Operation. · High Output Drive current. · 3.3V +10%/-5% Core power supply · 2.5V or 3.3V I/O supply. · LBO pin for linear or interleaved burst mode. · Internal input resistors on mode pins allow floating mode pins. · Default to Interleaved Pipelined Mode. · Byte write (BW) and/or global write (GW) operation. · Common data inputs and data outputs. · Clock Control, registered, address, data, and control. · Internal Self-Timed Write cycle. · Automatic power-down for portable applications. · JEDEC standard 100-lead TQFP or QFP package. -150 P i p e l i n e t C y c l e 6.6ns 3-1-1-1 tKQ 3.8ns IDD 270mA Flow tCycle 1 0 . 5 n s Through tKQ 9ns 2-1-1-1 IDD 170mA -138 -133 -117 -100 -66 7.25ns 7 . 5 n s 8.5ns 1 0 n s 12.5ns 4ns 4ns 4.5 5ns 6ns 245mA 240mA 2 1 0 m A 180mA 150mA 15ns 15ns 15ns 15ns 20ns 9.7ns 10ns 11ns 12ns 18ns 120mA 120mA 1 2 0 m A 120mA 95mA
64K x 32 2M Synchronous Burst SRAM
Flow Through / Pipeline Reads
150Mhz - 66Mhz 9ns - 18ns 3.3V VDD 3.3V & 2.5V I/O
The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FPBGA). Holding the FT mode pin/bump low, places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register.
Pipelined Reads
The GS820H32A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS820H32A is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU's, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS820H32A operates on a 3.3V power supply and all inputs/ outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit.
Controls
Addresses, data I/O's, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Rev: 1.04 3/2000 1/23 © 2000, Giga Semiconductor, Inc.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A 100 Pin TQFP and QFP Pinout
NC DQ C8 DQ C7 V DDQ V SS DQ C6 DQ C5 DQC4 DQ C3 V SS VDDQ DQC2 DQ C1 FT VDD NC VSS DQD1 DQ D2 VDDQ VSS DQD3 DQ D4 DQ D5 DQ D6 V SS VDDQ DQ D7 DQ D8 NC
100 99 98 9 7 96 95 94 9 3 92 91 90 8 9 88 87 86 8 5 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 64K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 4 9 50
CK GW BW G AD SC AD SP A DV A8 A9
A6 A7 E1 E2 BD BC BB BA E3 VDD V SS
NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC
Rev: 1.04 3/2000
LBO A5 A4
A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A12 A13 A14 A15 2/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NC
© 2000, Giga Semiconductor, Inc.
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GS820H32AT/Q-150/138/133/117/100/66
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 87 93, 94 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
Symbol
A0, A1 A2-15 DQ A1-DQA8 DQ B1-DQB8 D Q C 1 -DQC 8 D Q D 1 -DQD 8 NC BW BA, BB BC, BD CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO V DD V SS VDDQ
Type
I I
Description
Address field LSB's and Address Counter preset Inputs Address Inputs
I/O
Data Input and Output pins. No Connect
I I I I I I I I I I I I I I I I
Byte Write. Writes all enabled bytes. Active Low. Byte Write Enable for DQA, DQB Data I/O's. Active Low. Byte Write Enable for DQC, DQD Data I/O's. Active Low. Clock Input Signal. Active High. Global Write Enable. Writes all bytes. Active Low. Chip Enable. Active Low. Chip Enable. Active High. Output Enable. Active Low. Burst address counter advance enable. Active Low. Address Strobe (Processor, Cache Controller). Active Low. Sleep Mode control. Active High. Flow Through or Pipeline mode. Active Low. Linear Burst Order mode. Active Low. Core power supply. I/O and Core Ground. Output driver power supply.
H
Rev: 1.04 3/2000
3/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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